The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG) consists of:

• Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)
• Two auxiliary 32-bit load/store RISC CPU cores — Auxiliary Programmable Real-Time Units (RTU_PRU0 and RTU_PRU1)
• Data RAMs per PRU core
• Instruction RAMs per PRU and per RTU_PRU cores
• Shared RAM
• Peripheral modules: UART0, ECAP0, PWM, IEP0 and IEP1
• Interrupt controller (INTC)

The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device.

The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate independently or in coordination with each other and can also work in coordination with the device-level host CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU’s instruction memory.