米6体育平台手机版

ZHCSLA7C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

Table 6-7, Table 6-8, Figure 6-6, Figure 6-7, and Figure 6-8 present the reset timing requirements and switching characteristics.

Table 6-7 Reset Timing Requirements

NO.	PARAMETER	DESCRIPTION	MIN	UNIT
PORz Pin
RST1	t_w(PORzL)	Pulse Width minimum, PORz low	2000	ns
RST2	t_{h(SUPPLIES VALID - PORz)}	Hold time, PORz active (low) after all supplies valid	2000000	ns
RESETz Pin
RST5	t_w(RESETzL)	Pulse Width minimum, RESETz low	400	ns
MCU_PORz Pin
RST13	t_{w(MCU_PORzL)}	Pulse Width minimum, MCU_PORz	2000	ns
RST8	t_{h(SUPPLIES VALID - MCU_PORz)}	Hold time, MCU_PORz active (low) after all supplies valid	2000000	ns
MCU_RESETz Pin
RST9	t_{w(MCU_RESETzL)}	Pulse Width minimum, MCU_RESETz	400	ns
MCU_BYP_POR Pin
RST12	t_{su(MCU_BYP_POR-MCU_PORz)}	Setup time, MCU_BYP_POR active (high) before all supplies are valid	1000000	ns

Table 6-8 Reset Switching Characteristics

NO.	PARAMETER	DESCRIPTION	MIN	UNIT
PORz Pin
RST3	t_{d(PORz-PORz_OUT low)}	Delay time, PORz active (low) to PORz_OUT active (low)	0	ns
RST4	t_{d(PORz-PORz_OUT high)}	Delay time, PORz inactive (high) to PORz_OUT inactive (high)	0	ns
RESETz Pin
RST6	t_{d(RESETz-RESETSTATz low)}	Delay time, RESETz active (low) to RESETSTATz active (low)	4106	ns
RST7	t_{d(RESETz-RESETSTATz high)}	Delay time, RESETz inactive (high) to RESETSTATz inactive (high)	380000	ns
MCU_RESETSTATz Pin
RST10	t_{d(MCU_RESETz-MCU_RESETSTATz low)}	Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low)	4106	ns
RST11	t_{d(MCU_RESETz-MCU_RESETSTATz high)}	Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high)	289000	ns
MCU_PORz Pin
RST14	t_{d(MCU_PORz-MCU_PORz_OUT low)}	Delay time, MCU_PORz active (low) to MCU_PORz_OUT active (low)	0	ns
RST15	t_{d(MCU_PORz-MCU_PORz_OUT high)}	Delay time, MCU_PORz inactive (high) to MCU_PORz_OUT inactive (high)	0	ns

Figure 6-6 PORz Reset Timing

Figure 6-7 RESETz and RESETSTATz Timing

Figure 6-8 MCU_RESETz and MCU_RESETSTATz Timing

Table 6-9 and Figure 6-9 present the boot configuration timing requirements.

Table 6-9 Boot Configuration Timing Requirements

NO.	PARAMETER		MIN	UNIT
BC1	t_{su(BOOTMODE-PORz)}	Setup time, All Bootmode pins active to PORz inactive (high)	2000	ns
BC2	t_{h(PORz - BOOTMODE)}	Hold time, All Bootmode pins active after PORz inactive (high)	0	ns
BC3	t_{su(MCU_BOOTMODE-MCU_PORz)}	Setup time, All Bootmode pins active to MCU_PORz inactive (high)	2000	ns
BC4	t_{h(MCU_PORz - MCU_BOOTMODE)}	Hold time, All Bootmode pins active after MCU_PORz inactive (high)	0	ns

Figure 6-9 Boot Configuration Timing