ZHCSRW0A February   2023  – August 2023 AM68 , AM68A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
          1.        22
          2.        23
      4. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
          1.        26
        2. 6.3.3.2 WKUP Domain
          1.        28
      5. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
          1.        31
          2.        32
          3.        33
          4.        34
          5.        35
          6.        36
          7.        37
        2. 6.3.4.2 MCU Domain
          1.        39
          2.        40
        3. 6.3.4.3 WKUP Domain
          1.        42
      6. 6.3.5  I3C
        1. 6.3.5.1 MCU Domain
          1.        45
      7. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
          11.        58
          12.        59
          13.        60
          14.        61
          15.        62
          16.        63
          17.        64
          18.        65
        2. 6.3.6.2 MCU Domain
          1.        67
          2.        68
      8. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
          1.        71
          2.        72
          3.        73
          4.        74
          5.        75
          6.        76
          7.        77
        2. 6.3.7.2 MCU Domain
          1.        79
          2.        80
      9. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
          1.        83
          2.        84
          3.        85
          4.        86
          5.        87
          6.        88
          7.        89
          8.        90
          9.        91
          10.        92
        2. 6.3.8.2 MCU Domain
          1.        94
        3. 6.3.8.3 WKUP Domain
          1.        96
      10. 6.3.9  MDIO
        1. 6.3.9.1 MAIN Domain
          1.        99
        2. 6.3.9.2 MCU Domain
          1.        101
      11. 6.3.10 CPSW2G
        1. 6.3.10.1 MAIN Domain
          1.        104
        2. 6.3.10.2 MCU Domain
          1.        106
      12. 6.3.11 ECAP
        1. 6.3.11.1 MAIN Domain
          1.        109
          2.        110
          3.        111
      13. 6.3.12 EQEP
        1. 6.3.12.1 MAIN Domain
          1.        114
          2.        115
          3.        116
      14. 6.3.13 EPWM
        1. 6.3.13.1 MAIN Domain
          1.        119
          2.        120
          3.        121
          4.        122
          5.        123
          6.        124
          7.        125
      15. 6.3.14 USB
        1. 6.3.14.1 MAIN Domain
          1.        128
      16. 6.3.15 Display Port
        1. 6.3.15.1 MAIN Domain
          1.        131
      17. 6.3.16 Hyperlink
        1. 6.3.16.1 MAIN Domain
          1.        134
          2.        135
          3.        136
      18. 6.3.17 PCIE
        1. 6.3.17.1 MAIN Domain
          1.        139
      19. 6.3.18 SERDES
        1. 6.3.18.1 MAIN Domain
          1.        142
      20. 6.3.19 DSI
        1. 6.3.19.1 MAIN Domain
          1.        145
          2.        146
      21. 6.3.20 CSI
        1. 6.3.20.1 MAIN Domain
          1.        149
          2.        150
      22. 6.3.21 MCASP
        1. 6.3.21.1 MAIN Domain
          1.        153
          2.        154
          3.        155
          4.        156
          5.        157
      23. 6.3.22 DMTIMER
        1. 6.3.22.1 MAIN Domain
          1.        160
        2. 6.3.22.2 MCU Domain
          1.        162
      24. 6.3.23 CPTS
        1. 6.3.23.1 MAIN Domain
          1.        165
        2. 6.3.23.2 MCU Domain
          1.        167
      25. 6.3.24 DSS
        1. 6.3.24.1 MAIN Domain
          1.        170
      26. 6.3.25 GPMC
        1. 6.3.25.1 MAIN Domain
          1.        173
      27. 6.3.26 MMC
        1. 6.3.26.1 MAIN Domain
          1.        176
          2.        177
      28. 6.3.27 OSPI
        1. 6.3.27.1 MCU Domain
          1.        180
          2.        181
      29. 6.3.28 Hyperbus
        1. 6.3.28.1 MCU Domain
          1.        184
      30. 6.3.29 Emulation and Debug
        1. 6.3.29.1 MAIN Domain
          1.        187
          2.        188
      31. 6.3.30 System and Miscellaneous
        1. 6.3.30.1 Boot Mode configuration
          1.        191
        2. 6.3.30.2 Clock
          1.        193
          2.        194
        3. 6.3.30.3 System
          1.        196
          2.        197
        4. 6.3.30.4 EFUSE
          1.        199
        5. 6.3.30.5 VMON
          1.        201
      32. 6.3.31 Power
        1.       203
    4. 6.4 Connection for Unused Pins
  8. 7 Specifications
    1. 7.1  绝对最大额定值
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power-On-Hour (POH) Limits
    5. 7.5  Operating Performance Points
    6. 7.6  Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.6.7  ADC12B Electrical Characteristics
      8. 7.6.8  LVCMOS Electrical Characteristics
      9. 7.6.9  USB2PHY Electrical Characteristics
      10. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 7.6.11 UFS M-PHY Electrical Characteristics
      12. 7.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 7.6.13 DDR0 Electrical Characteristics
    7. 7.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8  Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics for ALZ Package
    9. 7.9  Temperature Sensor Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  CPSW2G
          1. 7.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.2.2 CPSW2G RMII Timings
            1. 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.2.3 CPSW2G RGMII Timings
            1. 7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  eCAP
          1. 7.10.5.6.1 Timing Requirements for eCAP
          2. 7.10.5.6.2 Switching Characteristics for eCAP
        7. 7.10.5.7  EPWM
          1. 7.10.5.7.1 Timing Requirements for eHRPWM
          2. 7.10.5.7.2 Switching Characteristics for eHRPWM
        8. 7.10.5.8  eQEP
          1. 7.10.5.8.1 Timing Requirements for eQEP
          2. 7.10.5.8.2 Switching Characteristics for eQEP
        9. 7.10.5.9  GPIO
          1. 7.10.5.9.1 GPIO Timing Requirements
          2. 7.10.5.9.2 GPIO Switching Characteristics
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.10.4 GPMC0 IOSET
        11. 7.10.5.11 HyperBus
          1. 7.10.5.11.1 Timing Requirements for HyperBus
          2. 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 7.10.5.12 I2C
        13. 7.10.5.13 I3C
        14. 7.10.5.14 MCAN
        15. 7.10.5.15 MCASP
        16. 7.10.5.16 MCSPI
          1. 7.10.5.16.1 MCSPI — Controller Mode
          2. 7.10.5.16.2 MCSPI — Peripheral Mode
        17. 7.10.5.17 MMCSD
          1. 7.10.5.17.1 MMC0 - eMMC Interface
            1. 7.10.5.17.1.1 Legacy SDR Mode
            2. 7.10.5.17.1.2 High Speed SDR Mode
            3. 7.10.5.17.1.3 High Speed DDR Mode
            4. 7.10.5.17.1.4 HS200 Mode
            5. 7.10.5.17.1.5 HS400 Mode
          2. 7.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.17.2.1 Default Speed Mode
            2. 7.10.5.17.2.2 High Speed Mode
            3. 7.10.5.17.2.3 UHS–I SDR12 Mode
            4. 7.10.5.17.2.4 UHS–I SDR25 Mode
            5. 7.10.5.17.2.5 UHS–I SDR50 Mode
            6. 7.10.5.17.2.6 UHS–I DDR50 Mode
            7. 7.10.5.17.2.7 UHS–I SDR104 Mode
        18. 7.10.5.18 CPTS
          1. 7.10.5.18.1 CPTS Timing Requirements
          2. 7.10.5.18.2 CPTS Switching Characteristics
        19. 7.10.5.19 OSPI
          1. 7.10.5.19.1 OSPI0 PHY Mode
            1. 7.10.5.19.1.1 OSPI With Data Training
              1. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training
            2. 7.10.5.19.1.2 OSPI Without Data Training
              1. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 7.10.5.19.2 OSPI0 Tap Mode
            1. 7.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 7.10.5.20 PCIE
        21. 7.10.5.21 Timers
          1. 7.10.5.21.1 Timing Requirements for Timers
          2. 7.10.5.21.2 Switching Characteristics for Timers
        22. 7.10.5.22 UART
          1. 7.10.5.22.1 Timing Requirements for UART
          2. 7.10.5.22.2 UART Switching Characteristics
        23. 7.10.5.23 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  9. 8 Detailed Description
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.1.1.1 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG and EMU
      4. 9.1.4 Reset
      5. 9.1.5 Unused Pins
      6. 9.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal Flash devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 工具与软件
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 支持资源
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALZ|770
散热焊盘机械数据 (封装 | 引脚)
订购信息

Table 6-114 Power Supply Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]ALZ PIN [4]
CAP_VDDS0 (1)CAPExternal Capacitor ConnectionT21
CAP_VDDS0_MCU (1)CAPExternal Capacitor ConnectionJ20
CAP_VDDS1_MCU (1)CAPExternal Capacitor ConnectionG16
CAP_VDDS2 (1)CAPExternal Capacitor ConnectionP21
CAP_VDDS2_MCU (1)CAPExternal Capacitor ConnectionH17
CAP_VDDS5 (1)CAPExternal Capacitor ConnectionM22
VDDAR_COREPWRCore RAM SupplyN17, V11, V16, Y20
VDDAR_CPUPWRCPU RAM SupplyH9, K14, P11, P14, V13
VDDAR_MCUPWRMCU RAM SupplyK17, K19
VDDA_0P8_DSITXPWRAnalog Supply for DSITXAB14
VDDA_0P8_DSITX_CPWRDSITX Clock SupplyAB15
VDDA_0P8_USBPWRUSB 0.8V SupplyAB8
VDDA_0P8_CSIRX0_1PWRAnalog Supply for CSIRXAB17, AB18
VDDA_0P8_DLL_MMC0PWRMMC DLL Analog SupplyW7
VDDA_0P8_PLL_DDR0PWRDDR de-skew PLL Analog SupplyP10
VDDA_0P8_PLL_DDR1PWRDDR de-skew PLL Analog SupplyJ14
VDDA_0P8_SERDES0_1PWRSERDES 0.8V SupplyAB10, AB11
VDDA_0P8_SERDES_C0_1PWRSERDES 0.8V Clock SupplyAA10, AA11
VDDA_1P8_DSITXPWRAnalog Supply for DSITXAA14, AA15
VDDA_1P8_USBPWRUSB 1.8V SupplyAB7
VDDA_1P8_CSIRX0_1PWRAnalog Supply for CSIRXAA17, AA19
VDDA_1P8_SERDES0_1PWRSERDES 1.8V SupplyAA12
VDDA_1P8_SERDES2_4PWRSERDES 1.8V SupplyAB13
VDDA_3P3_USBPWRUSB 3.3V SupplyAB9
VDDA_ADC0PWRADC0 Analog SupplyJ21
VDDA_ADC1PWRADC1 Analog SupplyK21
VDDA_MCU_PLLGRP0PWRAnalog Supply for MCU PLL Group 0K22
VDDA_MCU_TEMPPWRAnalog Supply for MCU temperature sensorJ17
VDDA_OSC1PWRHFOSC1 SupplyL21
VDDA_PLLGRP0PWRAnalog Supply for MAIN PLL Group 0U18
VDDA_PLLGRP1PWRAnalog Supply for MAIN PLL Group 1V19
VDDA_PLLGRP2PWRAnalog Supply for MAIN PLL Group 2Y11
VDDA_PLLGRP5PWRAnalog Supply for MAIN PLL Group 5N14
VDDA_PLLGRP6PWRAnalog Supply for MAIN PLL Group 6R12
VDDA_PLLGRP7PWRAnalog Supply for MAIN PLL Group 7R11
VDDA_PLLGRP8PWRAnalog Supply for MAIN PLL Group 8K12
VDDA_PLLGRP9PWRAnalog Supply for MAIN PLL Group 9T18
VDDA_PLLGRP10PWRAnalog Supply for MAIN PLL Group 10Y16
VDDA_PLLGRP12PWRAnalog Supply for MAIN PLL Group 12Y18
VDDA_PLLGRP13PWRAnalog Supply for MAIN PLL Group 13V12
VDDA_POR_WKUPPWRWKUP domain Analog SupplyL20
VDDA_TEMP0PWRAnalog Supply for temperature sensor 0U19
VDDA_TEMP1PWRAnalog Supply for temperature sensor 1K10
VDDA_TEMP2PWRAnalog Supply for temperature sensor 2T16
VDDA_TEMP3PWRAnalog Supply for temperature sensor 3U10
VDDA_TEMP4PWRAnalog Supply for temperature sensor 4Y14
VDDA_WKUPPWROscillator Supply for WKUP domainJ22
VDDSHV0PWRIO Power SupplyR21, U21, U22
VDDSHV0_MCUPWRIO Power SupplyH19, H20
VDDSHV1_MCUPWRIO Power SupplyH16, J16
VDDSHV2PWRIO Power SupplyM20, R20
VDDSHV2_MCUPWRIO Power SupplyG18, H18
VDDSHV5PWRIO Power SupplyM21, N22
VDDS_DDRPWRDDR PHY IO SupplyA1, A18, AA1, G10, G12, G14, G6, H11, H13, H15, J6, L6, N6, N9, P7, P8, R6, U9
VDDS_DDR_C0PWRIO Power Supply for DDR ClockR9
VDDS_DDR_C1PWRIO Power Supply for DDR ClockJ12
VDDS_MMC0PWRMMC0 PHY IO SupplyY7, Y8
VDD_COREPWRMAIN domain core SupplyAA21, AB20, J13, J15, M16, M19, N10, P18, R17, R19, T10, T20, U15, U17, U8, V14, V18, V20, V7, V9, W10, W13, W15, W17, W19, W21, W8, Y12, Y22, Y9
VDD_CPUPWRCPU core SupplyG8, H7, J8, K11, K13, K7, K9, L8, M14, M7, M9, N11, N15, P16, R13, R15, T12, T14, U11, U13
VDD_MCUPWRMCU core SupplyK16, K18, L15, L17, L19
VDD_MCU_WAKE1PWRCore Supply for MCU daisy chainJ19
VDD_WAKE0PWRCore Supply for MAIN domain daisy chainP20
VSSGNDGroundA14, A5, AA13, AA16, AA18, AA20, AA22, AA3, AA5, AA7, AA9, AB12, AB16, AB19, AB2, AB21, AB23, AB4, AB6, AC11, AC22, AC26, AC3, AC5, AC7, AC8, AD15, AD18, AD21, AD6, AD9, AE10, AE14, AE17, AE20, AE23, AE4, AE7, AF12, AF15, AF18, AF21, AF24, AF5, AF8, AG10, AG14, AG17, AG20, AG23, AG4, AG7, AH1, AH12, AH15, AH18, AH21, AH24, AH3, AH6, AH9, B11, B13, B15, B17, B2, B23, B4, B6, B8, C1, C12, C14, C16, C18, C3, C5, C7, D11, D13, D15, D17, D2, D4, D6, D8, E1, E12, E14, E16, E26, E3, E5, E7, F2, F4, F6, G13, G28, G3, G5, G7, G9, H10, H12, H14, H2, H21, H4, H6, H8, J1, J11, J18, J24, J3, J5, J7, J9, K15, K2, K20, K27, K4, K6, K8, L14, L16, L3, L5, L7, L9, M15, M17, M2, M25, M4, M6, M8, N1, N16, N18, N21, N23, N3, N7, P15, P17, P19, P22, P6, P9, R10, R14, R16, R18, R23, R26, R7, T11, T13, T15, T17, T19, T2, T22, T4, T6, T9, U12, U14, U16, U20, U23, U3, U5, U7, V10, V15, V17, V2, V21, V24, V4, V6, V8, W1, W11, W12, W14, W16, W18, W20, W22, W26, W3, W6, W9, Y10, Y13, Y15, Y17, Y19, Y2, Y21, Y23, Y4, Y6
(1) This pin must always be connected via a 1-μF ±10% capacitor to VSS.
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