ZHCSRW0A February   2023  – August 2023 AM68 , AM68A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
          1.        22
          2.        23
      4. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
          1.        26
        2. 6.3.3.2 WKUP Domain
          1.        28
      5. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
          1.        31
          2.        32
          3.        33
          4.        34
          5.        35
          6.        36
          7.        37
        2. 6.3.4.2 MCU Domain
          1.        39
          2.        40
        3. 6.3.4.3 WKUP Domain
          1.        42
      6. 6.3.5  I3C
        1. 6.3.5.1 MCU Domain
          1.        45
      7. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
          11.        58
          12.        59
          13.        60
          14.        61
          15.        62
          16.        63
          17.        64
          18.        65
        2. 6.3.6.2 MCU Domain
          1.        67
          2.        68
      8. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
          1.        71
          2.        72
          3.        73
          4.        74
          5.        75
          6.        76
          7.        77
        2. 6.3.7.2 MCU Domain
          1.        79
          2.        80
      9. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
          1.        83
          2.        84
          3.        85
          4.        86
          5.        87
          6.        88
          7.        89
          8.        90
          9.        91
          10.        92
        2. 6.3.8.2 MCU Domain
          1.        94
        3. 6.3.8.3 WKUP Domain
          1.        96
      10. 6.3.9  MDIO
        1. 6.3.9.1 MAIN Domain
          1.        99
        2. 6.3.9.2 MCU Domain
          1.        101
      11. 6.3.10 CPSW2G
        1. 6.3.10.1 MAIN Domain
          1.        104
        2. 6.3.10.2 MCU Domain
          1.        106
      12. 6.3.11 ECAP
        1. 6.3.11.1 MAIN Domain
          1.        109
          2.        110
          3.        111
      13. 6.3.12 EQEP
        1. 6.3.12.1 MAIN Domain
          1.        114
          2.        115
          3.        116
      14. 6.3.13 EPWM
        1. 6.3.13.1 MAIN Domain
          1.        119
          2.        120
          3.        121
          4.        122
          5.        123
          6.        124
          7.        125
      15. 6.3.14 USB
        1. 6.3.14.1 MAIN Domain
          1.        128
      16. 6.3.15 Display Port
        1. 6.3.15.1 MAIN Domain
          1.        131
      17. 6.3.16 Hyperlink
        1. 6.3.16.1 MAIN Domain
          1.        134
          2.        135
          3.        136
      18. 6.3.17 PCIE
        1. 6.3.17.1 MAIN Domain
          1.        139
      19. 6.3.18 SERDES
        1. 6.3.18.1 MAIN Domain
          1.        142
      20. 6.3.19 DSI
        1. 6.3.19.1 MAIN Domain
          1.        145
          2.        146
      21. 6.3.20 CSI
        1. 6.3.20.1 MAIN Domain
          1.        149
          2.        150
      22. 6.3.21 MCASP
        1. 6.3.21.1 MAIN Domain
          1.        153
          2.        154
          3.        155
          4.        156
          5.        157
      23. 6.3.22 DMTIMER
        1. 6.3.22.1 MAIN Domain
          1.        160
        2. 6.3.22.2 MCU Domain
          1.        162
      24. 6.3.23 CPTS
        1. 6.3.23.1 MAIN Domain
          1.        165
        2. 6.3.23.2 MCU Domain
          1.        167
      25. 6.3.24 DSS
        1. 6.3.24.1 MAIN Domain
          1.        170
      26. 6.3.25 GPMC
        1. 6.3.25.1 MAIN Domain
          1.        173
      27. 6.3.26 MMC
        1. 6.3.26.1 MAIN Domain
          1.        176
          2.        177
      28. 6.3.27 OSPI
        1. 6.3.27.1 MCU Domain
          1.        180
          2.        181
      29. 6.3.28 Hyperbus
        1. 6.3.28.1 MCU Domain
          1.        184
      30. 6.3.29 Emulation and Debug
        1. 6.3.29.1 MAIN Domain
          1.        187
          2.        188
      31. 6.3.30 System and Miscellaneous
        1. 6.3.30.1 Boot Mode configuration
          1.        191
        2. 6.3.30.2 Clock
          1.        193
          2.        194
        3. 6.3.30.3 System
          1.        196
          2.        197
        4. 6.3.30.4 EFUSE
          1.        199
        5. 6.3.30.5 VMON
          1.        201
      32. 6.3.31 Power
        1.       203
    4. 6.4 Connection for Unused Pins
  8. 7 Specifications
    1. 7.1  绝对最大额定值
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power-On-Hour (POH) Limits
    5. 7.5  Operating Performance Points
    6. 7.6  Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.6.7  ADC12B Electrical Characteristics
      8. 7.6.8  LVCMOS Electrical Characteristics
      9. 7.6.9  USB2PHY Electrical Characteristics
      10. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 7.6.11 UFS M-PHY Electrical Characteristics
      12. 7.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 7.6.13 DDR0 Electrical Characteristics
    7. 7.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8  Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics for ALZ Package
    9. 7.9  Temperature Sensor Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  CPSW2G
          1. 7.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.2.2 CPSW2G RMII Timings
            1. 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.2.3 CPSW2G RGMII Timings
            1. 7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  eCAP
          1. 7.10.5.6.1 Timing Requirements for eCAP
          2. 7.10.5.6.2 Switching Characteristics for eCAP
        7. 7.10.5.7  EPWM
          1. 7.10.5.7.1 Timing Requirements for eHRPWM
          2. 7.10.5.7.2 Switching Characteristics for eHRPWM
        8. 7.10.5.8  eQEP
          1. 7.10.5.8.1 Timing Requirements for eQEP
          2. 7.10.5.8.2 Switching Characteristics for eQEP
        9. 7.10.5.9  GPIO
          1. 7.10.5.9.1 GPIO Timing Requirements
          2. 7.10.5.9.2 GPIO Switching Characteristics
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.10.4 GPMC0 IOSET
        11. 7.10.5.11 HyperBus
          1. 7.10.5.11.1 Timing Requirements for HyperBus
          2. 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 7.10.5.12 I2C
        13. 7.10.5.13 I3C
        14. 7.10.5.14 MCAN
        15. 7.10.5.15 MCASP
        16. 7.10.5.16 MCSPI
          1. 7.10.5.16.1 MCSPI — Controller Mode
          2. 7.10.5.16.2 MCSPI — Peripheral Mode
        17. 7.10.5.17 MMCSD
          1. 7.10.5.17.1 MMC0 - eMMC Interface
            1. 7.10.5.17.1.1 Legacy SDR Mode
            2. 7.10.5.17.1.2 High Speed SDR Mode
            3. 7.10.5.17.1.3 High Speed DDR Mode
            4. 7.10.5.17.1.4 HS200 Mode
            5. 7.10.5.17.1.5 HS400 Mode
          2. 7.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.17.2.1 Default Speed Mode
            2. 7.10.5.17.2.2 High Speed Mode
            3. 7.10.5.17.2.3 UHS–I SDR12 Mode
            4. 7.10.5.17.2.4 UHS–I SDR25 Mode
            5. 7.10.5.17.2.5 UHS–I SDR50 Mode
            6. 7.10.5.17.2.6 UHS–I DDR50 Mode
            7. 7.10.5.17.2.7 UHS–I SDR104 Mode
        18. 7.10.5.18 CPTS
          1. 7.10.5.18.1 CPTS Timing Requirements
          2. 7.10.5.18.2 CPTS Switching Characteristics
        19. 7.10.5.19 OSPI
          1. 7.10.5.19.1 OSPI0 PHY Mode
            1. 7.10.5.19.1.1 OSPI With Data Training
              1. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training
            2. 7.10.5.19.1.2 OSPI Without Data Training
              1. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 7.10.5.19.2 OSPI0 Tap Mode
            1. 7.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 7.10.5.20 PCIE
        21. 7.10.5.21 Timers
          1. 7.10.5.21.1 Timing Requirements for Timers
          2. 7.10.5.21.2 Switching Characteristics for Timers
        22. 7.10.5.22 UART
          1. 7.10.5.22.1 Timing Requirements for UART
          2. 7.10.5.22.2 UART Switching Characteristics
        23. 7.10.5.23 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  9. 8 Detailed Description
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.1.1.1 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG and EMU
      4. 9.1.4 Reset
      5. 9.1.5 Unused Pins
      6. 9.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal Flash devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 工具与软件
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 支持资源
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALZ|770
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4 Connection for Unused Pins

This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls.

Note:

All power balls must be supplied with the voltages specified in the Recommended Operating Conditions section, unless otherwise specified in Signal Descriptions.

Note:

For additional clarification, "left unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball number.

Table 6-115 shows the connectivity requirements for specific signals by ball name and ball number.

Table 6-115 Connectivity Requirements
BALL
NUMBER		 BALL NAME CONNECTION REQUIREMENT
H28 WKUP_OSC0_XI Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level, if unused.
M28 OSC1_XI
B28 TRSTN
G1 DDR0_DQS0P
L1 DDR0_DQS1P
V1 DDR0_DQS2P
AB1 DDR0_DQS3P
A16 DDR1_DQS0P
A13 DDR1_DQS1P
A6 DDR1_DQS2P
A3 DDR1_DQS3P
T8 DDR0_RET
J10 DDR1_RET
H23 VMON1_ER_VSYS
L18 VMON6_IR_VEXT0P8
L22 VMON3_IR_VEXT1P8
M18 VMON2_IR_VCPU
N19 VMON4_IR_VEXT1P8
N20 VMON5_IR_VEXT3P3
L25 MCU_ADC0_AIN0 Each of these balls can be connected to VSS through a separate external pull resistor or can be connected directly to VSS to ensure these balls are held to a valid logic low-level, if unused.
K25 MCU_ADC0_AIN1
M24 MCU_ADC0_AIN2
L24 MCU_ADC0_AIN3
L27 MCU_ADC0_AIN4
K24 MCU_ADC0_AIN5
M27 MCU_ADC0_AIN6
M26 MCU_ADC0_AIN7
P25 MCU_ADC1_AIN0
R25 MCU_ADC1_AIN1
P28 MCU_ADC1_AIN2
P27 MCU_ADC1_AIN3
N25 MCU_ADC1_AIN4
P26 MCU_ADC1_AIN5
N26 MCU_ADC1_AIN6
N27 MCU_ADC1_AIN7
AC10 SERDES0_REXT Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level, if unused. Refer to Signal Descriptions footnote for appropriate value of pull-resistor for each signal.
AC18 CSI0_RXRCALIB
AC21 CSI1_RXRCALIB
R8 DDR0_CAL0
E8 DDR1_CAL0
AC13 DSI0_TXRCALIB
AC15 DSI1_TXRCALIB
AA6 USB0_RCALIB
A26 MCU_RESETZ Each of these balls must be connected to the corresponding power supply through a separate external pull resistor to ensure these balls are held to a valid logic high level, if unused.
G23 MCU_PORZ
K23 PORZ
A24 RESET_REQZ
A25 TCK
AG27 TMS
G24 MCU_I2C0_SCL
H24 WKUP_I2C0_SCL
H27 WKUP_I2C0_SDA
J25 MCU_I2C0_SDA
AE24 I2C0_SDA
AH25 I2C0_SCL
AG24 EXTINTN
AG28 TDI
AE26 TDO
A27 EMU0
C26 EMU1
H1 DDR0_DQS0N
M1 DDR0_DQS1N
U1 DDR0_DQS2N
AC1 DDR0_DQS3N
A15 DDR1_DQS0N
A12 DDR1_DQS1N
A7 DDR1_DQS2N
A2 DDR1_DQS3N
H22 VPP_MCU Each of these balls must be left unconnected, if unused.
V22 VPP_CORE
AF1 MMC0_CALPAD
DDR0_*

DDRSS0 and DDRSS1 must always be used in incremental order. For instance, when using a single LPDDR component, it must be

connected to the DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_* and DDR1_* interfaces.
DDR1_*

Table 6-116 shows the specific connection requirements for the RESERVED ball numbers on the device.

Note:

For additional clarification, "left unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers.

Table 6-116 Reserved Balls Specific Connection Requirements
BALL NUMBERS CONNECTION REQUIREMENTS
AB22 / AC12 / AC14 / AC16 / AC17 / AC19 / AC20 / AC23 / AD10 / AD11 / AD12 / AD5 / AE11 / F13 / G11 / G21 / H25 / K28 / L23 / L26 / N28 / N8 / T7 RESERVED.
These balls must be left unconnected.
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