The device provides several system clock outputs. Summary of these output clocks are as follows:
- MCU_CLKOUT0
- Reference clock output
for Ethernet PHYs (50 MHz or 25 MHz)
- MCU_SYSCLKOUT0
- MCU_SYSCLK0 is divided by
4 and then sent out of the device as a LVCMOS clock signal
(MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock
is functioning or not. This signal should not be used as a clock source
for external devices on a board.
- MCU_OBSCLK0
- On the clock output
MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and
debug. This signal should not be used as a clock source for external
devices on a board.
- SYSCLKOUT0
- SYSCLK0 is divided by 4
and then sent out of the device as a LVCMOS clock signal (SYSCLKOUT0).
This signal can be used to test if the main chip clock is functioning or
not. This signal should not be used as a clock source for external
devices on a board.
- CLKOUT
- Reference clock output
for Ethernet PHYs (50 MHz)
- OBSCLK[1:0]
- On the clock output
OBSCLK0/1, oscillators and PLLs clocks can be observed for tests and
debug.