ZHCSG74B april 2017 – april 2023 AMC1301-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
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6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety-Related Certifications
- 6.8 Safety Limiting Values
- 6.9 Electrical Characteristics
- 6.10 Switching Characteristics
- 6.11 Timing Diagram
- 6.12 Insulation Characteristics Curves
- 6.13 Typical Characteristics
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
8.2.2.3 Differential to Single-Ended Output Conversion
Figure 8-3 shows an example of a TLV900x-Q1-based signal conversion and filter circuit for systems using single-ended input ADCs to convert the analog output voltage into digital. For R1 = R3 and R2 = R4, the output voltage equals (R2 / R1) × (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ and C1 = C2 = 330 pF yields good performance.
Figure 8-3 Connecting the AMC1301-Q1 Output to a Single-Ended Input ADCFor more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.