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ZHCSCZ0F June 2014 – March 2017 AMC1305L25 , AMC1305M05 , AMC1305M25

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DW|16
- MSOI003I

散热焊盘机械数据 (封装 | 引脚)

DW|16
- QFND505A

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, AVDD to AGND or DVDD to DGND	–0.3	6.5	V
Analog input voltage at AINP, AINN	AGND – 6	AVDD + 0.5	V
Digital input voltage at CLKIN, CLKIN_N	DGND – 0.5	DVDD + 0.5	V
Input current to any pin except supply pins	–10	10	mA
Maximum virtual junction temperature, T_J		150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
AVDD	High-side (analog) supply voltage	4.5	5.0	5.5	V
DVDD	Controller-side (digital) supply voltage	3.0	3.3	5.5	V
T_A	Operating ambient temperature range	–40		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		AMC1305x	UNIT
		DW (SOIC)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	80.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	40.5	°C/W
R_θJB	Junction-to-board thermal resistance	45.1	°C/W
ψ_JT	Junction-to-top characterization parameter	11.9	°C/W
ψ_JB	Junction-to-board characterization parameter	44.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Ratings

PARAMETER		TEST CONDITIONS	VALUE	UNIT
P_D	Maximum power dissipation (both sides)	AVDD = 5.5 V, DVDD = 5.5 V, LVDS, R_LOAD = 100 Ω	89.1	mW
P_D1	Maximum power dissipation (high-side supply)	AVDD = 5.5 V	45.1	mW
P_D2	Maximum power dissipation (low-side supply)	DVDD = 5.5 V, LVDS, R_LOAD = 100 Ω	44	mW

7.6 Insulation Specifications

PARAMETER		TEST CONDITIONS	VALUE	UNIT
GENERAL
CLR	Minimum air gap (clearance)⁽¹⁾	Shortest pin-to-pin distance through air	≥ 8	mm
CPG	Minimum external tracking (creepage)⁽¹⁾	Shortest pin-to-pin distance across the package surface	≥ 8	mm
DTI	Distance through insulation	Minimum internal gap (internal clearance) of the double insulation (2 × 0.0135 mm)	0.027	mm
CTI	Comparative tracking index	DIN EN 60112 (VDE 0303-11); IEC 60112	≥ 600	V
	Material group	According to IEC 60664-1	I
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 300 V_RMS	I-IV
		Rated mains voltage ≤ 600 V_RMS	I-III
		Rated mains voltage ≤ 1000 V_RMS	I-II
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage	At ac voltage (bipolar or unipolar)	1414	V_PK
V_IOWM	Maximum-rated isolation working voltage	At ac voltage (sine wave)	1000	V_RMS
V_IOWM	Maximum-rated isolation working voltage	At dc voltage	1500	V_DC
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM, t = 60 s (qualification test)	7000	V_PK
V_IOTM	Maximum transient isolation voltage	V_TEST = 1.2 x V_IOTM, t = 1 s (100% production test)	8400	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50-μs waveform, V_TEST = 1.6 x V_IOSM = 10000 V_PK (qualification)	6250	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a, after input/output safety test subgroup 2 / 3, V_ini = V_IOTM, t_ini = 60 s, V_pd(m) = 1.2 x V_IORM = 1697 V_PK, t_m = 10 s	≤ 5	pC
		Method a, after environmental tests subgroup 1, V_ini = V_IOTM, t_ini = 60 s, V_pd(m) = 1.6 x V_IORM = 2263 V_PK, t_m = 10 s	≤ 5	pC
		Method b1, at routine test (100% production) and preconditioning (type test), V_ini = V_IOTM, t_ini = 1 s, V_pd(m) = 1.875 x V_IORM = 2652 V_PK, t_m = 1 s	≤ 5	pC
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.5 V_PP at 1 MHz	1.2	pF
R_IO	Insulation resistance, input to output⁽⁵⁾	V_IO = 500 V at T_S = 150°C	> 10⁹	Ω
	Pollution degree		2
	Climatic category		40/125/21
UL1577
V_ISO	Withstand isolation voltage	V_TEST = V_ISO = 5000 V_RMS or 7000 V_DC, t = 60 s (qualification test), V_TEST = 1.2 x V_ISO = 6000 V_RMS, t = 1 s (100% production test)	5000	V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves or ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

7.7 Safety-Related Certifications

VDE		UL
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60095 (VDE 0860): 2005-11		Recognized under UL1577 component recognition and CSA component acceptance NO 5 programs
Reinforced insulation		Single protection
File number: 40040142		File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
I_S	Safety input, output, or supply current	θ_JA = 80.2°C/W, AVDD = DVDD = 5.5 V, T_J = 150°C, T_A = 25°C, see Figure 3	283	mA
I_S	Safety input, output, or supply current	θ_JA = 80.2°C/W, AVDD = DVDD = 3.6 V, T_J = 150°C, T_A = 25°C, see Figure 3	432	mA
P_S	Safety input, output, or total power	θ_JA = 80.2°C/W, T_J = 150°C, T_A = 25°C, see Figure 4	1558⁽¹⁾	mW
T_S	Maximum safety temperature		150	°C

(1) Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics: AMC1305M05

All minimum and maximum specifications at T_A = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc³ filter with OSR = 256, unless otherwise noted. Typical values are at T_A = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_Clipping	Maximum differential voltage input range (AINP-AINN)			±62.5		mV
FSR	Specified linear full-scale range (AINP-AINN)		–50		50	mV
V_CM	Operating common-mode input range		–0.032		AVDD – 2	V
C_ID	Differential input capacitance			2		pF
I_IB	Input current	Inputs shorted to AGND	–97	–72	-57	μA
R_ID	Differential input resistance			5		kΩ
I_OS	Input offset current			±5		nA
CMTI	Common-mode transient immunity		15			kV/μs
CMRR	Common-mode rejection ratio	f_IN = 0 Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–104		dB
CMRR	Common-mode rejection ratio	f_IN from 0.1 Hz to 50 kHz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–75		dB
BW	Input bandwidth			800		kHz
DC ACCURACY
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
INL	Integral nonlinearity⁽³⁾	Resolution: 16 bits	–4	±1.5	4	LSB
E_O	Offset error	Initial, at 25°C	–50	±2.5	50	µV
TCE_O	Offset error thermal drift⁽¹⁾		–1.3		1.3	μV/°C
E_G	Gain error	Initial, at 25°C	–0.3%	–0.02%	0.3%
TCE_G	Gain error thermal drift⁽²⁾		–40	±20	40	ppm/°C
PSRR	Power-supply rejection ratio	V_AVDD from 4.5 to 5.5V, at dc		105		dB
AC ACCURACY
SNR	Signal-to-noise ratio	f_IN = 1 kHz	76	81		dB
SINAD	Signal-to-noise + distortion	f_IN = 1 kHz	76	81		dB
THD	Total harmonic distortion	f_IN = 1 kHz		–90	–83	dB
SFDR	Spurious-free dynamic range	f_IN = 1 kHz	83	92		dB
DIGITAL INPUTS/OUTPUTS
External Clock
f_CLKIN	Input clock frequency		5	20	20.1	MHz
Duty_CLKIN	Duty cycle	5 MHz ≤ f_CLKIN ≤ 20.1 MHz	40%	50%	60%
CMOS Logic Family, CMOS with Schmitt-Trigger
I_IN	Input current	DGND ≤ V_IN ≤ DVDD	–1		1	μA
C_IN	Input capacitance			5		pF
V_IH	High-level input voltage		0.7 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × DVDD	V
C_LOAD	Output load capacitance	f_CLKIN = 20 MHz		30		pF
V_OH	High-level output voltage	I_OH = –20 µA	DVDD – 0.1			V
V_OH	High-level output voltage	I_OH = –4 mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 20 µA			0.1	V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
POWER SUPPLY
AVDD	High-side supply voltage		4.5	5.0	5.5	V
I_AVDD	High-side supply current			6.5	8.2	mA
P_AVDD	High-side power dissipation			32.5	45.1	mW
DVDD	Controller-side supply voltage		3.0	3.3	5.5	V
I_DVDD	Controller-side supply current	3.0 V ≤ DVDD ≤ 3.6 V		2.7	4.0	mA
I_DVDD	Controller-side supply current	4.5 V ≤ DVDD ≤ 5.5 V		3.2	5.5	mA
P_DVDD	Controller-side power dissipation	3.0 V ≤ DVDD ≤ 3.6 V		8.9	14.4	mW
P_DVDD	Controller-side power dissipation	4.5 V ≤ DVDD ≤ 5.5 V		16.0	30.3	mW

(1) Offset error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_eodrift_bas654.gif

AMC1305L25 AMC1305M05 AMC1305M25 ec_eodrift_bas654.gif

(2) Gain error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_egdrift_bas654.gif

AMC1305L25 AMC1305M05 AMC1305M25 ec_egdrift_bas654.gif

(3) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

7.10 Electrical Characteristics: AMC1305x25

All minimum and maximum specifications at T_A = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = 0 V, and sinc³ filter with OSR = 256, unless otherwise noted. Typical values are at T_A = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_Clipping	Maximum differential voltage input range (AINP-AINN)			±312.5		mV
FSR	Specified linear full-scale range (AINP-AINN)		–250		250	mV
V_CM	Operating common-mode input range		–0.16		AVDD – 2	V
C_ID	Differential input capacitance			1		pF
I_IB	Input current	Inputs shorted to AGND	–82	–60	–48	μA
R_ID	Differential input resistance			25		kΩ
I_OS	Input offset current			±5		nA
CMTI	Common-mode transient immunity		15			kV/μs
CMRR	Common-mode rejection ratio	f_IN = 0 Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–95		dB
CMRR	Common-mode rejection ratio	f_IN from 0.1 Hz to 50 kHz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–76		dB
BW	Input bandwidth			1000		kHz
DC ACCURACY
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
INL	Integral nonlinearity⁽¹⁾	Resolution: 16 bits	–4	±1.5	4	LSB
E_O	Offset error	Initial, at 25°C	–150	±40	150	µV
TCE_O	Offset error thermal drift⁽²⁾		–1.3		1.3	μV/°C
E_G	Gain error	Initial, at 25°C	–0.3	–0.02	0.3	%FS
TCE_G	Gain error thermal drift⁽³⁾		–40	±20	40	ppm/°C
PSRR	Power-supply rejection ratio	V_AVDD from 4.5 V to 5.5 V, at dc		90		dB
AC ACCURACY
SNR	Signal-to-noise ratio	f_IN = 1 kHz	82	85		dB
SINAD	Signal-to-noise + distortion	f_IN = 1 kHz	80	84		dB
THD	Total harmonic distortion	f_IN = 1 kHz		–90	–83	dB
SFDR	Spurious-free dynamic range	f_IN = 1 kHz	83	92		dB
DIGITAL INPUTS/OUTPUTS
External Clock
f_CLKIN	Input clock frequency		5	20	20.1	MHz
Duty_CLKIN	Duty cycle	5 MHz ≤ f_CLKIN ≤ 20.1 MHz	40%	50%	60%
CMOS Logic Family (AMC1305M25), CMOS with Schmitt-Trigger
I_IN	Input current	DGND ≤ V_IN ≤ DVDD	–1		1	μA
C_IN	Input capacitance			5		pF
V_IH	High-level input voltage		0.7 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × DVDD	V
C_LOAD	Output load capacitance	f_CLKIN = 20 MHz		30		pF
V_OH	High-level output voltage	I_OH = –20 µA	DVDD – 0.1			V
V_OH	High-level output voltage	I_OH = –4 mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 20 µA			0.1	V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
LVDS Logic Family (AMC1305L25)
V_OD	Differential output voltage	R_LOAD = 100 Ω	250	350	450	mV
V_OCM	Output common-mode voltage		1.125	1.23	1.375	V
I_S	Output short-circuit current				24	mA
V_ICM	Input common-mode voltage	V_ID = 100 mV	0.05	1.25	3.25	V
V_ID	Differential input voltage		100	350	600	mV
I_IN	Input current	DGND ≤ V_IN ≤ 3.3 V	–24	0	20	µA
POWER SUPPLY
AVDD	High-side supply voltage		4.5	5.0	5.5	V
I_AVDD	High-side supply current			6.5	8.2	mA
P_AVDD	High-side power dissipation			32.5	45.1	mW
DVDD	Controller-side supply voltage		3.0	3.3	5.5	V
I_DVDD	Controller-side supply current	AMC1305L25, R_LOAD = 100 Ω		6.1	8.0	mA
		AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V, C_LOAD = 5 pF		2.7	4.0
		AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V, C_LOAD = 5 pF		3.2	5.5
P_DVDD	Controller-side power dissipation	AMC1305L25, R_LOAD = 100 Ω		20.1	44.0	mW
		AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V, C_LOAD = 5 pF		8.9	14.4
		AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V, C_LOAD = 5 pF		16.0	30.3

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or as a percent of the specified linear full-scale range FSR.

(2) Offset error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_eodrift_bas654.gif

(3) Gain error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_egdrift_bas654.gif

7.11 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
t_CLK	CLKIN, CLKIN_N clock period	49.75	50	200	ns
t_HIGH	CLKIN, CLKIN_N clock high time	19.9	25	120	ns
t_LOW	CLKIN, CLKIN_N clock low time	19.9	25	120	ns
t_D	Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay, C_LOAD = 5 pF	0		15	ns
t_ISTART	Interface startup time (DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V)	32		32	CLKIN cycles
t_ASTART	Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V)		1		ms

AMC1305L25 AMC1305M05 AMC1305M25 tim_int_bas654.gif

Figure 1. Digital Interface Timing

AMC1305L25 AMC1305M05 AMC1305M25 tim_start_bas654.gif

Figure 2. Digital Interface Startup Timing

7.12 Insulation Characteristics Curves

AMC1305L25 AMC1305M05 AMC1305M25 D043_SBAS654.gif

Figure 3. Thermal Derating Curve for Safety Limiting Current per VDE

AMC1305L25 AMC1305M05 AMC1305M25 Figure 3.gif

T_A up to 150°C, stress voltage frequency = 60 Hz

Figure 5. Reinforced Isolation Capacitor Lifetime Projection

AMC1305L25 AMC1305M05 AMC1305M25 D044_SBAS655.gif

Figure 4. Thermal Derating Curve for Safety Limiting Power per VDE

7.13 Typical Characteristics

At T_A = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN = 20 MHz, and sinc³ filter with OSR = 256, unless otherwise noted.

AMC1305L25 AMC1305M05 AMC1305M25 D001_SBAS654.gif

Figure 6. Input Current vs Input Common-Mode Voltage

AMC1305L25 AMC1305M05 AMC1305M25 D003_SBAS654.gif

Figure 8. Integral Nonlinearity vs Input Signal Amplitude

AMC1305L25 AMC1305M05 AMC1305M25 D005_SBAS654.gif

AMC1305x25

Figure 10. Offset Error vs High-Side Supply Voltage

AMC1305L25 AMC1305M05 AMC1305M25 D007_SBAS654.gif

AMC1305x25

Figure 12. Offset Error vs Temperature

AMC1305L25 AMC1305M05 AMC1305M25 D009_SBAS654.gif

Figure 14. Offset Error vs Clock Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D011_SBAS654.gif

Figure 16. Gain Error vs Temperature

AMC1305L25 AMC1305M05 AMC1305M25 D013_SBAS654.gif

Figure 18. Power-Supply Rejection Ratio vs
Ripple Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D015_SBAS654.gif

Figure 20. SNR and SINAD vs Temperature

AMC1305L25 AMC1305M05 AMC1305M25 D017_SBAS654.gif

Figure 22. SNR and SINAD vs Input Signal Frequency

AMC1305M05

Figure 24. SNR and SINAD vs Input Signal Amplitude

Figure 26. Total Harmonic Distortion vs Temperature

AMC1305L25 AMC1305M05 AMC1305M25 D023_SBAS654.gif

Figure 28. Total Harmonic Distortion vs
Input Signal Frequency

AMC1305M05

Figure 30. Total Harmonic Distortion vs
Input Signal Amplitude

Figure 32. Spurious-Free Dynamic Range vs Temperature

AMC1305L25 AMC1305M05 AMC1305M25 D029_SBAS654.gif

Figure 34. Spurious-Free Dynamic Range vs
Input Signal Frequency

AMC1305M05

Figure 36. Spurious-Free Dynamic Range vs
Input Signal Amplitude

AMC1305x25, 4096-point FFT, V_IN = 500 mV_PP

Figure 38. Frequency Spectrum with 5-kHz Input Signal

AMC1305L25 AMC1305M05 AMC1305M25 D035_SBAS654.gif

AMC1305M05, 4096-point FFT, V_IN = 500 mV_PP

Figure 40. Frequency Spectrum with 5-kHz Input Signal

AMC1305L25 AMC1305M05 AMC1305M25 D037_SBAS654.gif

Figure 42. High-Side Supply Current vs Temperature

AMC1305L25 AMC1305M05 AMC1305M25 D039_SBAS654.gif

Figure 44. Controller-Side Supply Current vs
Controller-Side Supply Voltage (3.3 V, nom)

AMC1305L25 AMC1305M05 AMC1305M25 D041_SBAS654.gif

Figure 46. Controller-Side Supply Current vs Temperature

AMC1305L25 AMC1305M05 AMC1305M25 D002_SBAS654.gif

Figure 7. Common-Mode Rejection Ratio vs
Input Signal Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D004_SBAS654.gif

Figure 9. Integral Nonlinearity vs Temperature

AMC1305M05

Figure 11. Offset Error vs High-Side Supply Voltage

AMC1305M05

Figure 13. Offset Error vs Temperature

Figure 15. Gain Error vs High-Side Supply Voltage

AMC1305L25 AMC1305M05 AMC1305M25 D012_SBAS654.gif

Figure 17. Gain Error vs Clock Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D014_SBAS654.gif

Figure 19. SNR and SINAD vs High-Side Supply Voltage

AMC1305L25 AMC1305M05 AMC1305M25 D016_SBAS654.gif

Figure 21. SNR and SINAD vs Clock Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D018_SBAS654.gif

AMC1305x25

Figure 23. SNR and SINAD vs Input Signal Amplitude

AMC1305L25 AMC1305M05 AMC1305M25 D020_SBAS654.gif

Figure 25. Total Harmonic Distortion vs
High-Side Supply Voltage

AMC1305L25 AMC1305M05 AMC1305M25 D022_SBAS654.gif

Figure 27. Total Harmonic Distortion vs Clock Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D024_SBAS654.gif

AMC1305x25

Figure 29. Total Harmonic Distortion vs
Input Signal Amplitude

AMC1305L25 AMC1305M05 AMC1305M25 D026_SBAS654.gif

Figure 31. Spurious-Free Dynamic Range vs
High-Side Supply Voltage

AMC1305L25 AMC1305M05 AMC1305M25 D028_SBAS654.gif

Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D030_SBAS654.gif

AMC1305x25

Figure 35. Spurious-Free Dynamic Range vs
Input Signal Amplitude

AMC1305L25 AMC1305M05 AMC1305M25 D032_SBAS654.gif

AMC1305x25, 4096-point FFT, V_IN = 500 mV_PP

Figure 37. Frequency Spectrum with 1-kHz Input Signal

AMC1305L25 AMC1305M05 AMC1305M25 D034_SBAS654.gif

AMC1305M05, 4096-point FFT, V_IN = 500 mV_PP

Figure 39. Frequency Spectrum with 1-kHz Input Signal

AMC1305L25 AMC1305M05 AMC1305M25 D036_SBAS654.gif

Figure 41. High-Side Supply Current vs
High-Side Supply Voltage

AMC1305L25 AMC1305M05 AMC1305M25 D038_SBAS654.gif

Figure 43. High-Side Supply Current vs Clock Frequency

AMC1305L25 AMC1305M05 AMC1305M25 D040_SBAS654.gif

Figure 45. Controller-Side Supply Current vs
Controller-Side Supply Voltage (5 V, nom)

AMC1305L25 AMC1305M05 AMC1305M25 D042_SBAS654.gif

Figure 47. Controller-Side Supply Current vs
Clock Frequency