ZHCSFZ3 February   2017 AMC1305L25-Q1 , AMC1305M05-Q1 , AMC1305M25-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: AMC1305M05-Q1
    10. 7.10 Electrical Characteristics: AMC1305x25-Q1
    11. 7.11 Switching Characteristics
    12. 7.12 Insulation Characteristics Curves
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Modulator
      3. 8.3.3 Digital Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Output
      2. 8.4.2 Output Behavior in Case of Full-Scale Input
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Filter Usage
    2. 9.2 Typical Applications
      1. 9.2.1 Traction Inverter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Isolated Voltage Sensing
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, AVDD to AGND or DVDD to DGND –0.3 6.5 V
Analog input voltage at AINP, AINN AGND – 6 AVDD + 0.5 V
Digital input voltage at CLKIN, CLKIN_N DGND – 0.3 DVDD + 0.3 V
Input current to any pin except supply pins –10 10 mA
Maximum virtual junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2500 V
Charged device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD High-side (analog) supply voltage 4.5 5.0 5.5 V
DVDD Controller-side (digital) supply voltage 3.0 3.3 5.5 V
TA Operating ambient temperature range –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) AMC1305x-Q1 UNIT
DW (SOIC)
16 PINS
RθJA Junction-to-ambient thermal resistance 80.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 40.5 °C/W
RθJB Junction-to-board thermal resistance 45.1 °C/W
ψJT Junction-to-top characterization parameter 11.9 °C/W
ψJB Junction-to-board characterization parameter 44.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Ratings

PARAMETER TEST CONDITIONS VALUE UNIT
PD Maximum power dissipation (both sides) AVDD = 5.5 V, DVDD = 5.5 V, LVDS, RLOAD = 100 Ω 89.1 mW
PD1 Maximum power dissipation (high-side supply) AVDD = 5.5 V 45.1 mW
PD2 Maximum power dissipation (low-side supply) DVDD = 5.5 V, LVDS, RLOAD = 100 Ω 44 mW

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR Minimum air gap (clearance)(1) Shortest pin-to-pin distance through air ≥ 8 mm
CPG Minimum external tracking (creepage)(1) Shortest pin-to-pin distance across the package surface ≥ 8 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation (2 × 0.0135 mm) 0.027 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-III
Rated mains voltage ≤ 1000 VRMS I-II
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12(2)
VIORM Maximum repetitive peak isolation voltage At ac voltage (bipolar or unipolar) 1414 VPK
VIOWM Maximum-rated isolation working voltage At ac voltage (sine wave) 1000 VRMS
At dc voltage 1500 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 7000 VPK
VTEST = 1.2 x VIOTM, t = 1 s (100% production test) 8400
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50-μs waveform, VTEST = 1.6 x VIOSM = 10000 VPK (qualification) 6250 VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroup 2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 x VIORM = 1697 VPK, tm = 10 s ≤ 5 pC
Method a, after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 x VIORM = 2263 VPK, tm = 10 s ≤ 5 pC
Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 x VIORM = 2652 VPK, tm = 1 s ≤ 5 pC
CIO Barrier capacitance, input to output(5) VIO = 0.5 VPP at 1 MHz 1.2 pF
RIO Insulation resistance, input to output(5) VIO = 500 V at TS = 150°C > 109 Ω
Pollution degree 2
Climatic category 40/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification test), VTEST = 1.2 x VISO = 6000 VRMS, t = 1 s (100% production test) 5000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves or ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.

7.7 Safety-Related Certifications

VDE UL
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60095 (VDE 0860): 2005-11 Recognized under UL1577 component recognition and CSA component acceptance NO 5 programs
Reinforced insulation Single protection
File number: 40040142 File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current θJA = 80.2°C/W, AVDD = DVDD = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3 283 mA
θJA = 80.2°C/W, AVDD = DVDD = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3 432 mA
PS Safety input, output, or total power θJA = 80.2°C/W, TJ = 150°C, TA = 25°C, see Figure 4 1558(1) mW
TS Maximum safety temperature 150 °C
(1) Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics: AMC1305M05-Q1

All minimum and maximum specifications at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VClipping Maximum differential voltage input range
(AINP-AINN)		 ±62.5 mV
FSR Specified linear full-scale range
(AINP-AINN)		 –50 50 mV
VCM Operating common-mode input range –0.032 AVDD – 2 V
CID Differential input capacitance 2 pF
IIB Input current Inputs shorted to AGND –97 –72 -57 μA
RID Differential input resistance 5 kΩ
IOS Input offset current ±5 nA
CMTI Common-mode transient immunity 15 kV/μs
CMRR Common-mode rejection ratio fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max 		–104 dB
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max 		–75
BW Input bandwidth 800 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity(3) Resolution: 16 bits –5 ±1.5 5 LSB
EO Offset error Initial, at 25°C –50 ±2.5 50 µV
TCEO Offset error thermal drift(1) –1.3 1.3 μV/°C
EG Gain error Initial, at 25°C –0.3% –0.02% 0.3%
TCEG Gain error thermal drift(2) –40 ±20 40 ppm/°C
PSRR Power-supply rejection ratio VAVDD from 4.5 to 5.5V, at dc 105 dB
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 76 81 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 76 81 dB
THD Total harmonic distortion fIN = 1 kHz –90 –83 dB
SFDR Spurious-free dynamic range fIN = 1 kHz 83 92 dB
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN Input clock frequency 5 20 20.1 MHz
DutyCLKIN Duty cycle 5 MHz ≤ fCLKIN ≤ 20.1 MHz 40% 50% 60%
CMOS Logic Family, CMOS with Schmitt-Trigger
IIN Input current DGND ≤ VIN ≤ DVDD –1 1 μA
CIN Input capacitance 5 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitance fCLKIN = 20 MHz 30 pF
VOH High-level output voltage IOH = –20 µA DVDD – 0.1 V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4
POWER SUPPLY
AVDD High-side supply voltage 4.5 5.0 5.5 V
IAVDD High-side supply current 6.5 8.2 mA
PAVDD High-side power dissipation 32.5 45.1 mW
DVDD Controller-side supply voltage 3.0 3.3 5.5 V
IDVDD Controller-side supply current 3.0 V ≤ DVDD ≤ 3.6 V 2.7 4.0 mA
4.5 V ≤ DVDD ≤ 5.5 V 3.2 5.5
PDVDD Controller-side power dissipation 3.0 V ≤ DVDD ≤ 3.6 V 8.9 14.4 mW
4.5 V ≤ DVDD ≤ 5.5 V 16.0 30.3
(1) Offset error drift is calculated using the box method as described by the following equation: AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 ec_eodrift_bas654.gif
(2) Gain error drift is calculated using the box method as described by the following equation: AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 ec_egdrift_bas654.gif
(3) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

7.10 Electrical Characteristics: AMC1305x25-Q1

All minimum and maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VClipping  Maximum differential voltage input range
(AINP-AINN)		 ±312.5 mV
FSR Specified linear full-scale range
(AINP-AINN)		 –250 250 mV
VCM  Operating common-mode input range    –0.16 AVDD – 2 V
CID  Differential input capacitance 1 pF
IIB  Input current Inputs shorted to AGND –82 –60 –48 μA
RID  Differential input resistance 25 kΩ
IOS  Input offset current ±5 nA
CMTI Common-mode transient immunity 15 kV/μs
CMRR Common-mode rejection ratio fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max 		–95 dB
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max 		–76
BW Input bandwidth 1000 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity(1) Resolution: 16 bits –4 ±1.5 4 LSB
EO  Offset error  Initial, at 25°C –150 ±40 150 µV
TCEO  Offset error thermal drift(2) –1.3 1.3 μV/°C
EG  Gain error  Initial, at 25°C –0.3 –0.02 0.3 %FS
TCEG  Gain error thermal drift(3) –40 ±20 40 ppm/°C
PSRR Power-supply rejection ratio VAVDD from 4.5 V to 5.5 V, at dc 90 dB
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 82 85 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 80 84 dB
THD Total harmonic distortion fIN = 1 kHz –90 –83 dB
SFDR Spurious-free dynamic range fIN = 1 kHz 83 92 dB
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN  Input clock frequency 5 20 20.1 MHz
DutyCLKIN  Duty cycle 5 MHz ≤ fCLKIN ≤ 20.1 MHz 40% 50% 60%
CMOS Logic Family (AMC1305M25-Q1), CMOS with Schmitt-Trigger
IIN  Input current DGND ≤ VIN ≤ DVDD –1 1 μA
CIN  Input capacitance 5 pF
VIH  High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL  Low-level input voltage –0.3 0.3 × DVDD V
CLOAD  Output load capacitance fCLKIN = 20 MHz 30 pF
VOH  High-level output voltage IOH = –20 µA DVDD – 0.1 V
IOH = –4 mA DVDD – 0.4
VOL  Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4
LVDS Logic Family (AMC1305L25-Q1)
VOD  Differential output voltage RLOAD = 100 Ω 250 350 450 mV
VOCM  Output common-mode voltage 1.125 1.23 1.375 V
IS  Output short-circuit current 24 mA
VICM  Input common-mode voltage VID = 100 mV 0.05 1.25 3.25 V
VID  Differential input voltage 100 350 600 mV
IIN  Input current DGND ≤ VIN ≤ 3.3 V –24 0 20 µA
POWER SUPPLY
AVDD High-side supply voltage 4.5 5.0 5.5 V
IAVDD  High-side supply current 6.5 8.2 mA
PAVDD  High-side power dissipation 32.5 45.1 mW
DVDD Controller-side supply voltage 3.0 3.3 5.5 V
IDVDD  Controller-side supply current AMC1305L25-Q1, RLOAD = 100 Ω 6.1 8.0 mA
AMC1305M25-Q1, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF		 2.7 4.0
AMC1305M25-Q1, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF		 3.2 5.5
PDVDD  Controller-side power dissipation AMC1305L25-Q1, RLOAD = 100 Ω 20.1 44.0 mW
AMC1305M25-Q1, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF		 8.9 14.4
AMC1305M25-Q1, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF		 16.0 30.3
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or as a percent of the specified linear full-scale range FSR.
(2) Offset error drift is calculated using the box method as described by the following equation: AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 ec_eodrift_bas654.gif
(3) Gain error drift is calculated using the box method as described by the following equation: AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 ec_egdrift_bas654.gif

7.11 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tCLK CLKIN, CLKIN_N clock period 49.75 50 200 ns
tHIGH CLKIN, CLKIN_N clock high time 19.9 25 120 ns
tLOW CLKIN, CLKIN_N clock low time 19.9 25 120 ns
tD Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay,
CLOAD = 5 pF		 0 15 ns
tISTART Interface startup time
(DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V)		 32 32 CLKIN cycles
tASTART Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V) 1 ms
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 tim_int_bas654.gif Figure 1. Digital Interface Timing
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 tim_start_bas654.gif Figure 2. Digital Interface Startup Timing

7.12 Insulation Characteristics Curves

AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D043_SBAS654.gif
Figure 3. Thermal Derating Curve for Safety Limiting Current per VDE
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 Figure 3.gif
TA up to 150°C, stress voltage frequency = 60 Hz
Figure 5. Reinforced Isolation Capacitor Lifetime Projection
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D044_SBAS655.gif
Figure 4. Thermal Derating Curve for Safety Limiting Power per VDE

7.13 Typical Characteristics

At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted.
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D001_SBAS797.gif
Figure 6. Input Current vs Input Common-Mode Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D003_SBAS654.gif
Figure 8. Integral Nonlinearity vs Input Signal Amplitude
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D005_SBAS654.gif
AMC1305x25-Q1
Figure 10. Offset Error vs High-Side Supply Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D007_SBAS654.gif
AMC1305x25-Q1
Figure 12. Offset Error vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D009_SBAS797.gif
Figure 14. Offset Error vs Clock Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D011_SBAS654.gif
Figure 16. Gain Error vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D013_SBAS797.gif
Figure 18. Power-Supply Rejection Ratio vs
Ripple Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D015_SBAS797.gif
Figure 20. SNR and SINAD vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D017_SBAS797.gif
Figure 22. SNR and SINAD vs Input Signal Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D019_SBAS654.gif
AMC1305M05-Q1
Figure 24. SNR and SINAD vs Input Signal Amplitude
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D021_SBAS654.gif
Figure 26. Total Harmonic Distortion vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D023_SBAS654.gif
Figure 28. Total Harmonic Distortion vs
Input Signal Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D025_SBAS654.gif
AMC1305M05-Q1
Figure 30. Total Harmonic Distortion vs
Input Signal Amplitude
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D027_SBAS654.gif
Figure 32. Spurious-Free Dynamic Range vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D029_SBAS654.gif
Figure 34. Spurious-Free Dynamic Range vs
Input Signal Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D031_SBAS654.gif
AMC1305M05-Q1
Figure 36. Spurious-Free Dynamic Range vs
Input Signal Amplitude
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D033_SBAS654.gif
AMC1305x25-Q1, 4096-point FFT, VIN = 500 mVPP
Figure 38. Frequency Spectrum with 5-kHz Input Signal
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D035_SBAS654.gif
AMC1305M05-Q1, 4096-point FFT, VIN = 500 mVPP
Figure 40. Frequency Spectrum with 5-kHz Input Signal
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D037_SBAS654.gif
Figure 42. High-Side Supply Current vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D039_SBAS654.gif
Figure 44. Controller-Side Supply Current vs
Controller-Side Supply Voltage (3.3 V, nom)
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D041_SBAS654.gif
Figure 46. Controller-Side Supply Current vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D002_SBAS797.gif
Figure 7. Common-Mode Rejection Ratio vs
Input Signal Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D004_SBAS654.gif
Figure 9. Integral Nonlinearity vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D006_SBAS654.gif
AMC1305M05-Q1
Figure 11. Offset Error vs High-Side Supply Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D008_SBAS654.gif
AMC1305M05-Q1
Figure 13. Offset Error vs Temperature
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D010_SBAS654.gif
Figure 15. Gain Error vs High-Side Supply Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D012_SBAS654.gif
Figure 17. Gain Error vs Clock Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D014_SBAS797.gif
Figure 19. SNR and SINAD vs High-Side Supply Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D016_SBAS797.gif
Figure 21. SNR and SINAD vs Clock Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D018_SBAS654.gif
AMC1305x25-Q1
Figure 23. SNR and SINAD vs Input Signal Amplitude
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D020_SBAS654.gif
Figure 25. Total Harmonic Distortion vs
High-Side Supply Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D022_SBAS654.gif
Figure 27. Total Harmonic Distortion vs Clock Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D024_SBAS654.gif
AMC1305x25-Q1
Figure 29. Total Harmonic Distortion vs
Input Signal Amplitude
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D026_SBAS654.gif
Figure 31. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D028_SBAS654.gif
Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D030_SBAS654.gif
AMC1305x25-Q1
Figure 35. Spurious-Free Dynamic Range vs
Input Signal Amplitude
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D032_SBAS654.gif
AMC1305x25-Q1, 4096-point FFT, VIN = 500 mVPP
Figure 37. Frequency Spectrum with 1-kHz Input Signal
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D034_SBAS654.gif
AMC1305M05-Q1, 4096-point FFT, VIN = 500 mVPP
Figure 39. Frequency Spectrum with 1-kHz Input Signal
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D036_SBAS654.gif
Figure 41. High-Side Supply Current vs
High-Side Supply Voltage
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D038_SBAS654.gif
Figure 43. High-Side Supply Current vs Clock Frequency
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D040_SBAS654.gif
Figure 45. Controller-Side Supply Current vs
Controller-Side Supply Voltage (5 V, nom)
AMC1305L25-Q1 AMC1305M05-Q1 AMC1305M25-Q1 D042_SBAS654.gif
Figure 47. Controller-Side Supply Current vs
Clock Frequency
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