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ZHCSG26C March 2017 – Janaury 2020 AMC1306E05 , AMC1306E25 , AMC1306M05 , AMC1306M25

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DWV|8

散热焊盘机械数据 (封装 | 引脚)

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7.11 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_CLKIN	CLKIN clock frequency	4.5 V ≤ AVDD ≤ 5.5 V	5		21	MHz
f_CLKIN	CLKIN clock frequency	3.0 V ≤ AVDD ≤ 5.5 V	5		20	MHz
t_CLKIN	CLKIN clock period	4.5 V ≤ AVDD ≤ 5.5 V	47.6		200	ns
t_CLKIN	CLKIN clock period	3.0 V ≤ AVDD ≤ 5.5 V	50		200	ns
t_HIGH	CLKIN clock high time		20	25	120	ns
t_LOW	CLKIN clock low time		20	25	120	ns
t_H	DOUT hold time after rising edge of CLKIN	AMC1306Mx⁽¹⁾, C_LOAD = 15 pF	3.5			ns
t_D	Rising edge of CLKIN to DOUT valid delay	AMC1306Mx⁽¹⁾, C_LOAD = 15 pF			15	ns
t_r	DOUT rise time	10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V, C_LOAD = 15 pF		0.8	3.5	ns
t_r	DOUT rise time	10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD = 15 pF		1.8	3.9	ns
t_f	DOUT fall time	90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V, C_LOAD = 15 pF		0.8	3.5	ns
t_f	DOUT fall time	90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD = 15 pF		1.8	3.9	ns
t_ISTART	Interface startup time	DVDD at 2.7 V (min) to DOUT valid with AVDD ≥ 3.0 V	32		32	CLKIN cycles
t_ASTART	Analog startup time	AVDD step to 3.0 V with DVDD ≥ 2.7 V, 0.1% settling		0.5		ms

(1) The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns; see the Manchester Coding Feature section for additional details.

AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 tim_int_bas734.gif

Figure 1. Digital Interface Timing

AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 tim_start_bas734.gif

Figure 2. Device Startup Timing