Place a differential RC filter (R1, R2, C5) in front of the isolated modulator to improve signal-to-noise performance of the signal path. Design the input filter such that:

• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (f_CLKIN) of the ΔΣ modulator
• The input bias current does not generate significant voltage drop across the DC impedances (R1, R2) of the input filter
• The impedances measured from the analog inputs are equal (R1 equals R2)

Capacitors C6 and C7 are optional and improve common-mode rejection at high frequencies (>1 MHz). For best performance, C6 must match the value of C7 and both capacitors must be 10 to 20 times lower in value than C5. For most applications, the structure shown in Figure 8-2 achieves excellent performance.

Figure 8-2 Differential Input Filter