SBASA51 May   2020 AMC1336-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1.  Absolute Maximum Ratings
    2. Table 2.  ESD Ratings
    3. Table 3.  Recommended Operating Conditions
    4. Table 4.  Thermal Information
    5. Table 5.  Power Ratings
    6. Table 6.  Insulation Specifications
    7. Table 7.  Safety-Related Certifications
    8. Table 8.  Safety Limiting Values
    9. Table 9.  Electrical Characteristics
    10. Table 10. Switching Characteristics
    11. 6.1       Insulation Characteristics Curves
    12. 6.2       Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Clock Input
      5. 7.3.5 Digital Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Behavior in Case of a Full-Scale Input
      2. 7.4.2 AVDD Diagnostics and Fail-Safe Output
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Input Filter Design
      4. 8.2.4 Application Curve
      5. 8.2.5 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Isolation Glossary
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Table 9. Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and fCLKIN = 20 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Single-ended input resistance AINN = AGND 0.1 1.5 GΩ
RIND Differential input resistance 0.16 1.5 GΩ
CIN Single-ended input capacitance AINN = AGND, fCLKIN = 20 MHz 2 pF
CIND Differential input capacitance fCLKIN = 20 MHz 2 pF
IIB Input bias current AINP = AINN = AGND; IIB = (IAINP + IAINN) / 2 –10 ±3 10 nA
TCIIB Input bias current drift AINP = AINN = AGND; IIB = (IAINP + IAINN) / 2 –14 pA/°C
IIO Input offset current IIO = IAINP – IAINN –5 ±1 5 nA
CMTI Common-mode transient immunity |AGND – DGND| = 1 kV 80 115 kV/µs
DC ACCURACY
Resolution Decimation filter output set to 16 bits 16 Bit
INL Integral nonlinearity(2) Resolution: 16 bits –4 ±1.6 4 LSB
EO Offset error Initial, at TA = 25°C, AINP = AINN = AGND –0.5 ±0.03 0.5 mV
TCEO Offset error drift(3) –4 ±0.6 4 µV/°C
EG Gain error(1) Initial, at TA = 25°C,
VAINP = 1 V or VAINN = –1 V, AINN = AGND		 –0.2 ±0.02 0.2 %
TCEG Gain error drift(4) –40 ±20 40 ppm/°C
CMRR Common-mode rejection ratio AINP = AINN, fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max –104 dB
AINP = AINN, fIN = 10 kHz, –0.5 V ≤ VIN ≤ 0.5 V –96
PSRR Power-supply rejection ratio PSRR vs AVDD, at DC –83 dB
PSRR vs AVDD, 100-mV and 10-kHz ripple –83
AC ACCURACY
SNR Signal-to-noise ratio VIN = 2 VPP, fIN = 1 kHz 82 87 dB
SINAD Signal-to-noise + distortion VIN = 2 VPP, fIN = 1 kHz 79 85 dB
THD Total harmonic distortion VIN = 2 VPP, fIN = 1 kHz; single-ended input (AINN = AGND = 0V) -91 -80 dB
VIN = 2 VPP, fIN = 1 kHz; Differential input over full CM range -92 -78 dB
SFDR Spurious-free dynamic range VIN = 2 VPP, fIN = 1 kHz 80 92 dB
DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)
IIN Input current DGND ≤ VIN ≤ DVDD 7 µA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 x DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 x DVDD V
DIGITAL OUTPUT (CMOS)
CLOAD Output load capacitance fCLKIN = 21 MHz 15 30 pF
VOH High-level output voltage IOH = –20 µA DVDD – 0.1 V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4
POWER SUPPLY
AVDDPOR AVDD power-on reset threshold voltage AVDD falling 2.4 2.6 2.8 V
IAVDD High-side supply current 3 V ≤ AVDD ≤ 3.6 V 6.8 9 mA
4.5 V ≤ AVDD ≤ 5.5 V 7.8 10.5
IDVDD Controller-side supply current 2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF 3.4 5 mA
4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF 3.7 6
(1) The typical value includes one sigma statistical variation.
(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(3) Offset error drift is calculated using the box method, as described by the following equation:
TCEO = (valueMAX - valueMIN) / TempRange
(4) Gain error drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((valueMAX - valueMIN) / (value x TempRange)) x 106.
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