When an out-of-limit event occurs, the proper flag bits in the status registers are set ('1'), and the corresponding interrupts are generated, if enabled. When an interrupt is generated, the SMBALERT pin asserts low. The host can poll the device status registers to get the information, or give a response to the SMBALERT interrupt signal. It is important to note how the SMBALERT output and status bits behave when writing interrupt-handler software. Figure 8-21 shows how the SMBALERT output and status bits behave.

Once a limit is exceeded, the corresponding status bit is set to '1'. The status bit remains set until the error condition subsides and the status register gets read. The status bits are referred to as being sticky because they remain set until read by software. This design ensures that out-of-limit events cannot be missed if the software is polling the device periodically. The SMBALERT output remains low for the entire duration that the reading is out of limits and remains low until the status register has been read. This architecture has implications on how software handles the interrupt.

Figure 8-21 SMBALERT Pin and Status Bits Behavior