The AMC6821-Q1 has the following temperature limitation detections:

1. High and Low Temperature Limit: The value of the High-Temp-Limit and Low-Temp-Limit registers specify the remote or local temperature ranges of normal operation. When the local or remote temperatures are equal to or above the value of the corresponding High-Temp-Limit register, the LTH or RTH bits in the status register are set ('1'). Likewise, when the local or remote temperatures are less than or equal to the corresponding Low-Temp-Limit register, the LTL or RTL bits in the status register are set ('1').

   When the local temperature is out-of-range (LTH = 1 or LTL = 1), the local temperature out-of-range event occurs. The LTO bit in the status register is set ('1'), and the LTO interrupt is generated via the SMBALERT pin if it is enabled (the LTOIE bit of Configuration Register 2 is set). Similarly, when the remote temperature is out-of range (RTH = 1 or RTL = 1), the remote temperature out-of-range event occurs. The RTO bit in the status register is set ('1'), and the RTO interrupt is generated via the SMBALERT pin if it is enabled (that is, the RTOIE bit of Configuration Register 2 is set).

2. Critical Limit: Critical temperature limit is the highest allowed of remote or local temperature. When the temperature is greater than or equal to the corresponding critical temperature, the LTCT or RTCT bit of the status register is set ('1'), the output of the OVR pin goes low, and a non-maskable interrupt is generated through the SMBALERT pin (low).
3. Passive Cooling Temperature (PSV) Limit: This limit defines the passive cooling threshold. In the auto remote-temperature-fan control mode, the system enters a passive cooling condition when the remote temperature is equal to or below this limit, and the fan stops. In the maximum fast speed calculated control mode, the fan stops and the system enters a passive cooling condition when both the remote and local temperatures are equal to or below this limit. In passive cooling, the LPSV bit of Status Register 2 (0x03) is set ('1'), and a PSV interrupt is generated on the SMBALERT pin if enabled (PSVIE = 1). Note that reading the Status Register clears the LPSV bit. After reading, if the active control temperature remains equal to or below the PSV temperature, this bit reasserts on next monitoring cycle.
4. THERM Limit: This limit is an additional fail-safe threshold. When the local or remote temperature is equal to or above this limit, the corresponding L-THERM or R-THERM bit is set ('1'), and the THERM pin is asserted low, which can be used to throttle the CPU clock. Furthermore, the THERM interrupt is generated on the SMBALERT pin if enabled (THERMOVIE = 1). Reading Status Register 1 clears the R-THERM and L-THERM bits. Once cleared, these bits are not reasserted until the temperature falls 5°C below the THERM limit, even if the THERM condition persists. If the THERM-FAN-EN bit of Configuration Register 3 is set ('1'), L-THERM = 1 or R-THERM = 1 forces the fan to run at full speed. When THERM-FAN-EN = 0, the status of the L-THERM and R-THERM bits do not affect the fan speed directly. Note that the THERM limit can be lower or higher than other temperature limits. For example, if the THERM limit is lower than the PSV temperature limit, then the CPU clock can be throttled while the cooling fan is off.

Figure 8-4 Temperature Out-of-Range Detection