The PWM-Out pin is an open-drain output. When PWM-EN of Configuration Register 2 is cleared ('0'), the PWM-Out pin is disabled and goes into a high-impedance status. When PWM-EN is set ('1'), the PWM-Out pin is enabled to drive the fan. When enabled, the status of the PWM-Out pin is determined by the PWM duty cycle and phase bits (PWMINV of Configuration Register 1). When PWMINV = 0 (default), the PWM-Out pin goes low for 100% duty cycle (suitable for driving the fan using a PMOS FET). Setting PWMINV to '1' makes the PWM-Out pin go high (with an external pull-up resistor) for a 100% duty cycle. This setting is used to drive an NMOS-power FET.

Figure 8-5 PWM Output