7.3.1 Block Level Description

The AMC80 continuously converts analog inputs to 10-bit resolution using a 2.5-mV least significant bit (LSB) with a default input range of 0 V to 2.56 V, or a 6-mV LSB with a programmable input range of 0 V to V+. The analog inputs (CH0 to CH6) are intended for connection to the several power supplies present in any typical system. Temperature can be converted to a 9-bit or 12-bit resolution with either 0.5°C or 0.0625°C LSB, respectively. The FAN1 and FAN2 inputs can be programmed to accept either a fan failure indicator or tachometer signals. Fan failure signals can be programmed to be either active high or active low. Fan inputs measure the period of tachometer pulses from the the fans, providing a higher count for lower fan speeds. The fan inputs are digital inputs with transition levels according to the Digital Inputs section of the Electrical Characteristics table. Full-scale fan counts are 255 (8-bit counter), which represent a stopped or very slow fan. Nominal speeds, based on a count of 153, are programmable from 1100 RPM to 8800 RPM. Signal conditioning circuitry is included to accommodate slow rise and fall times.

The AMC80 provides a number of internal registers:

• Configuration Register: Provides control and configuration.
• Interrupt Status Registers: Two registers that provide the status of each interrupt alarm.
• Interrupt Mask Registers: Allows masking of individual interrupt sources, as well as separate masking for both hardware interrupt outputs.
• Fan Divisor/RST_OUT/OS Register: Bits 0 to 5 of this register contain the divisor bits for the FAN1 and FAN2 inputs. Bits 6 and 7 control the function of the RST_OUT/OS output.
• OS Configuration/Temperature Resolution Register: The configuration of the overtemperature shutdown (OS) is controlled by the lower three bits of this register. Bit 3 enables 12-bit temperature conversions. In 12-bit mode, bits 4 to 7 represent the four LSBs of the temperature measurement. In 9-bit mode, bit 4 represents the LSB of the temperature measurement.
• Conversion Rate Register: Sets the time interval of the continuous monitoring cycle to either fixed or programmable (see the Conversion Rate Count Register for setting the programmable time interval).
• Voltage/Temperature Channel Disable Register: Allows voltage inputs and the local temperature conversion to be disabled.
• Input Mode Register: Allows voltage inputs to be configured as single-ended or as a differential pair with normal or reverse polarity.
• ADC Control Register: Bits 0 to 2 set the programmable conversion rate for the 10-bit ADC. Bits 3 to 5 allow for programmable input full-scale voltage.
• Conversion Rate Count Register: Selects the adjustable time interval when the conversion rate of the continuous monitoring cycle is set to programmable.
• Value RAM: The monitoring results (for temperature, voltages, fan counts, and Fan Divisor/RST_OUT/OS Register limits) are all contained in the Value RAM. The Value RAM consists of 32 bytes. The first 10 bytes are all of the results, the next 20 bytes are the interrupt alarm limits, and the last two bytes are at the upper locations for manufacturer ID and die revision ID.

The AMC80 SMBus is compatible with both fast mode (400 kHz) and high-speed mode (3.4 MHz) two-wire interface modes of operation. The AMC80 supports a timeout reset function on SDA and SCL that prevents two-wire bus lockup, and includes an analog filter on the two-wire digital control lines that improves noise immunity. Three address pins (A0 to A2), allow up to eight devices on a single bus. When enabled, the AMC80 starts by cycling through each measurement in sequence, and continuously loops through the sequence based on the Conversion Rate Register (address 07h) setting. Each measured value is compared to values stored in the Value RAM Registers (addresses 2Ah to 3Dh). When the measured value exceeds the programmed limit, the AMC80 sets a corresponding interrupt in the Interrupt Status Registers (addresses 01h and 02h). Two output interrupt lines (INT and RST_OUT/OS) are available. INT is fully programmable with the ability to mask each interrupt source and each output. The Fan Divisor/RST_OUT/OS Register (address 05h) has control bits that enable or disable the hardware interrupts. Additional digital inputs are provided for daisy-chaining the interrupt output pin, INT. This configuration is achieved by connecting multiple external temperature sensors (for example, the TMP75) to the board temperature interrupt (BTI) input and/or the GPI/CI input. The chassis intrusion (CI) input is designed to accept an active high signal from an external circuit that latches (for example, when the chassis from a server rack is removed).

7.3.2 Temperature Measurement

The AMC80 ΔV_BE-type temperature sensor, is a ΔΣ ADC that performs 9-bit or 12-bit twos complement temperature conversions. An 8-bit comparator that compares the readings to the user-programmable hot and overtemperature setpoints, and hysteresis values is also incorporated into the AMC80.

Temperature data can be read from the Temperature Reading Register (address 27h). Temperature limits can be read from and written to the Hot Temperature (T_HOT), Hot Temperature Hysteresis (T_{HOT_HYST}), OS Temperature (T_OS), and OS Temperature Hysteresis (T_{OS_HYST}) Limit Registers (addresses 38h to 3Bh). Each limit is represented in 12-bit, 9-bit, or 8-bit resolution, as shown in Table 1.

When using a single-byte read, the eight MSBs of the temperature reading can be found in the Value RAM Register (address 27h). The remainder of the temperature reading can be found in the OS Configuration/Temperature Resolution Register (address 06h), bits 4 to 7. In 9-bit format, bit 7 is the only valid bit. In addition, all nine or 12 bits can be read using a double-byte read at register address 27h.

There are four Value RAM Register limits for the temperature reading that affect the INT and OS outputs of the AMC80. These are the T_HOT, T_{HOT_HYST,} T_OS, T_{OS_HYST} Limit Registers (addresses 38h to 3Bh); see Table 15. There are three interrupt modes of operation: Default Interrupt, One-Time Interrupt, and Comparator. The OS output of the AMC80 can be programmed for One-Time Interrupt mode and Comparator mode. INT can be programmed for Default Interrupt mode and One-Time Interrupt mode. These modes are explained in the following subsections.

7.3.3 Interrupt Structure

Figure 7 depicts the interrupt structure of the AMC80.

Figure 7. Interrupt Structure

External interrupt inputs can come from the following sources:

• Board Temperature Interrupt (BTI) - This pin is an active low interrupt recommended to come from the overtemperature shutdown (OS) output of TMP75 temperature sensors. The TMP75 OS output activates when its temperature exceeds a programmed threshold. If the temperature of any TMP75 exceeds its programmed limit, BTI is driven low. This action generates an interrupt through bit 1 of Interrupt Status Register 2 (address 02h) that notifies the host of a possible overtemperature condition. To disable this feature, set bit 1 of Interrupt Mask Register 2 (address 04h) to high. This pin also provides an internal, 10-kΩ pull-up resistor.
• GPI/CI - This pin is an active high interrupt from any type of device that detects and captures chassis intrusion violations. This action could be accomplished mechanically, optically, or electrically; circuitry external to the AMC80 is expected to latch the event. Read this interrupt using bit 4 of Interrupt Status Register 2 (address 02h), and disable it using bit 4 of Interrupt Mask Register 2 (address 04h). The design of the AMC80 allows this input to go high even with no power applied, and no clamping or other interference with the line occurs. This line can also be pulled low by the AMC80 for at least 10ms to reset a typical chassis-intrusion circuit. Accomplish this reset by setting bit 5 of the Configuration Register (address 00h) to high; this bit is self-clearing.
• INT_IN - This pin is an active low interrupt that provides a way to connect an INT from other devices through the AMC80 to the processor. If this pin is pulled low, then bit 7 of Interrupt Status Register 1 (address 01h) goes high, indicating this interrupt detection. Setting bit 1 of the Configuration Register (address 00h) also allows the INT pin to go low when INT_IN goes low. To disable this feature, set bit 7 of Interrupt Mask Register 1 (address 03h) to high.

Device interrupt outputs can come from the following sources:

• INT - This pin becomes active whenever INT_IN, BTI, or GPI/CI interrupts. INT is enabled when bit 1 of the Configuration Register (address 00h) is set high. Bits 2 and 3 of the Configuration Register are also used to set the polarity and state of the INT interrupt line.
• OS - In the Fan Divisor/RST_OUT/OS Register (address 05h), bit 6 (OS Pin Enable), must be set high and bit 7 (RST Enable) must be set to low in order to enable the OS function on the RST_OUT/OS pin. The OS pin has two modes of operation: One-Time Interrupt and Comparator. One-Time Interrupt mode is selected by taking bit 2 of the OS Configuration/Temperature Resolution Register (address 06h) high. If bit 2 is taken low, then Comparator mode is selected. Unlike the OS pin, the OS bit in Interrupt Status Register 2 (address 02h, bit 5) functions in Default Interrupt and One-Time Interrupt modes. The OS bit can be masked to the INT pin by taking bit 5 in Interrupt Mask Register 2 (address 04h) low.

Reading the Interrupt Status Registers (addresses 01h to 02h) outputs the contents and then resets the registers and the INT pin. The INT pin is also cleared by the INT_Clear bit (address 00h, bit 3) without affecting the contents of the Interrupt Status Registers. When this bit is high, the AMC80 monitoring loop is inactive; monitoring resumes when this bit is low.

7.4.1 Interface and Control

The SMBus control lines in the AMC80 include SDA, SCL, and the A0 to A2 address pins, which allow up to eight AMC80 devices to be on the same bus. The AMC80 can only operate as a slave device. The SCL line controls only the serial interface; all other clock-related functions within the AMC80 (such as the ADC and fan counters) operate with a separate asynchronous internal clock. The default power-on SMBus address for the AMC80 is '0101'(A2)(A1)(A0) binary, where (A2)(A1)(A0) is the SMBus address.

When using the SMBus interface, a write command always consists of the AMC80 SMBus interface address byte, followed by the internal address register byte, and then the data byte (see Figure 8).

See Figure 9 for the read operation timing. There are two cases for a read operation:

1. If the contents of the Internal Address Register are known, simply read the AMC80 with the SMBus interface address byte, followed by the data byte read from the ADC80.
2. If the internal Address Register contents are unknown, write to the AMC80 with the SMBus interface address byte, followed by the internal address register bye. Then restart the serial communication with a read that consist of the SMBus interface address byte, followed by the data byte read from the AMC80.

1. The values of A0, A1, and A2 are determined by the A0, A1, and A2 pins, respectively.

Figure 8. Two-Wire Timing for Write Word Format

1. The values of A0, A1, and A2 are determined by the A0, A1, and A2 pins, respectively.

2. Master should leave SDA high to terminate a single-byte read operation.

3. Master should leave SDA high to terminate a two-byte read operation.

Figure 9. Two-Wire Timing for Read Word Format

7.5.1 Configuration Register

7.5.2 Interrupt Status Registers

7.5.3 Interrupt Mask Registers

7.5.4 Fan Divisor/RST_OUT/OS Register

7.5.5 OS Configuration/Temperature Resolution Register

7.5.6 Conversion Rate Register

7.5.7 Voltage/Temperature Channel Disable Register

7.5.8 Input Mode Register

7.5.9 ADC Control Register

7.5.10 Conversion Rate Count Register

7.5.11 Value Ram Register