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ZHCSFJ7C August 2016 – December 2018 AMIC110

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机械数据 (封装 | 引脚)

ZCZ|324

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Table 7-32 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode

NO.	PARAMETER		OPP100		OPP50		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
GNF0	t_w(wenV)	Pulse duration, output write enable gpmc_wen valid	A⁽¹⁾		A⁽¹⁾		ns
GNF1	t_d(csnV-wenV)	Delay time, output chip select gpmc_csn[x]⁽¹³⁾ valid to output write enable gpmc_wen valid	B⁽²⁾ – 0.2	B⁽²⁾ + 2.0	B⁽²⁾ – 5	B⁽²⁾ + 5	ns
GNF2	t_w(cleH-wenV)	Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle high to output write enable gpmc_wen valid	C⁽³⁾ – 0.2	C⁽³⁾ + 2.0	C⁽³⁾ – 5	C⁽³⁾ + 5	ns
GNF3	t_w(wenV-dV)	Delay time, output data gpmc_ad[15:0] valid to output write enable gpmc_wen valid	D⁽⁴⁾ – 0.2	D⁽⁴⁾ + 2.0	D⁽⁴⁾ – 5	D⁽⁴⁾ + 5	ns
GNF4	t_w(wenIV-dIV)	Delay time, output write enable gpmc_wen invalid to output data gpmc_ad[15:0] invalid	E⁽⁵⁾ – 0.2	E⁽⁵⁾ + 5	E⁽⁵⁾ – 5	E⁽⁵⁾ + 5	ns
GNF5	t_{w(wenIV-cleIV)}	Delay time, output write enable gpmc_wen invalid to output lower-byte enable and command latch enable gpmc_be0n_cle invalid	F⁽⁶⁾ – 0.2	F⁽⁶⁾ + 2.0	F⁽⁶⁾ – 5	F⁽⁶⁾ + 5	ns
GNF6	t_{w(wenIV-csnIV)}	Delay time, output write enable gpmc_wen invalid to output chip select gpmc_csn[x]⁽¹³⁾ invalid	G⁽⁷⁾ – 0.2	G⁽⁷⁾ + 2.0	G⁽⁷⁾ – 5	G⁽⁷⁾ + 5	ns
GNF7	t_w(aleH-wenV)	Delay time, output address valid and address latch enable gpmc_advn_ale high to output write enable gpmc_wen valid	C⁽³⁾ – 0.2	C⁽³⁾ + 2.0	C⁽³⁾ – 5	C⁽³⁾ + 5	ns
GNF8	t_{w(wenIV-aleIV)}	Delay time, output write enable gpmc_wen invalid to output address valid and address latch enable gpmc_advn_ale invalid	F⁽⁶⁾ – 0.2	F⁽⁶⁾ + 2.0	F⁽⁶⁾ – 5	F⁽⁶⁾ + 5	ns
GNF9	t_c(wen)	Cycle time, write		H⁽⁸⁾		H⁽⁸⁾	ns
GNF10	t_d(csnV-oenV)	Delay time, output chip select gpmc_csn[x]⁽¹³⁾ valid to output enable gpmc_oen valid	I⁽⁹⁾ – 0.2	I⁽⁹⁾ + 2.0	I⁽⁹⁾ – 5	I⁽⁹⁾ + 5	ns
GNF13	t_w(oenV)	Pulse duration, output enable gpmc_oen valid		K⁽¹⁰⁾		K⁽¹⁰⁾	ns
GNF14	t_c(oen)	Cycle time, read	L⁽¹¹⁾		L⁽¹¹⁾		ns
GNF15	t_{w(oenIV-csnIV)}	Delay time, output enable gpmc_oen invalid to output chip select gpmc_csn[x]⁽¹³⁾ invalid	M⁽¹²⁾ – 0.2	M⁽¹²⁾ + 2.0	M⁽¹²⁾ – 5	M⁽¹²⁾ + 5	ns

A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾
E = ((WrCycleTime – WEOffTime) × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾
F = ((ADVWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
G = ((CSWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾
I = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾
L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾
M = ((CSRdOffTime – OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

1. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.

Figure 7-28 GPMC and NAND Flash—Command Latch Cycle1

1. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.

Figure 7-29 GPMC and NAND Flash—Address Latch Cycle1

1. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field.

2. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

3. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.

Figure 7-30 GPMC and NAND Flash—Data Read Cycle123

1. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.

Figure 7-31 GPMC and NAND Flash—Data Write Cycle1