ZHCSFJ7C August   2016  – December 2018 AMIC110

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
      1. 4.1.1 ZCE Package Pin Maps (Top View)
      2. 4.1.2 ZCZ Package Pin Maps (Top View)
        1. Table 4-1 ZCZ Pin Map [Section Left - Top View]
        2. Table 4-2 ZCZ Pin Map [Section Middle - Top View]
        3. Table 4-3 ZCZ Pin Map [Section Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 External Memory Interfaces
      2. 4.3.2 General Purpose IOs
      3. 4.3.3 Miscellaneous
        1. 4.3.3.1 eCAP
        2. 4.3.3.2 eHRPWM
        3. 4.3.3.3 eQEP
        4. 4.3.3.4 Timer
      4. 4.3.4 PRU-ICSS
        1. 4.3.4.1 PRU0
        2. 4.3.4.2 PRU1
      5. 4.3.5 Removable Media Interfaces
      6. 4.3.6 Serial Communication Interfaces
        1. 4.3.6.1 CAN
        2. 4.3.6.2 GEMAC_CPSW
        3. 4.3.6.3 I2C
        4. 4.3.6.4 McASP
        5. 4.3.6.5 SPI
        6. 4.3.6.6 UART
        7. 4.3.6.7 USB
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points (OPPs)
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  Thermal Resistance Characteristics for ZCE and ZCZ Packages
    9. 5.9  External Capacitors
      1. 5.9.1 Voltage Decoupling Capacitors
        1. 5.9.1.1 Core Voltage Decoupling Capacitors
        2. 5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
      2. 5.9.2 Output Capacitors
    10. 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
  6. 6Power and Clocking
    1. 6.1 Power Supplies
      1. 6.1.1 Power Supply Slew Rate Requirement
      2. 6.1.2 Power-Down Sequencing
      3. 6.1.3 VDD_MPU_MON Connections
      4. 6.1.4 Digital Phase-Locked Loop Power Supply Requirements
    2. 6.2 Clock Specifications
      1. 6.2.1 Input Clock Specifications
      2. 6.2.2 Input Clock Requirements
        1. 6.2.2.1 OSC0 Internal Oscillator Clock Source
          1. Table 6-2 OSC0 Crystal Circuit Requirements
          2. Table 6-3 OSC0 Crystal Circuit Characteristics
        2. 6.2.2.2 OSC0 LVCMOS Digital Clock Source
        3. 6.2.2.3 OSC1 Internal Oscillator Clock Source
          1. Table 6-5 OSC1 Crystal Circuit Requirements
          2. Table 6-6 OSC1 Crystal Circuit Characteristics
        4. 6.2.2.4 OSC1 LVCMOS Digital Clock Source
        5. 6.2.2.5 OSC1 Not Used
      3. 6.2.3 Output Clock Specifications
      4. 6.2.4 Output Clock Characteristics
        1. 6.2.4.1 CLKOUT1
        2. 6.2.4.2 CLKOUT2
  7. 7Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  OPP50 Support
    4. 7.4  Controller Area Network (CAN)
      1. 7.4.1 DCAN Electrical Data and Timing
        1. Table 7-1 DCAN Timing Conditions
        2. Table 7-2 Timing Requirements for DCANx Receive
        3. Table 7-3 Switching Characteristics for DCANx Transmit
    5. 7.5  DMTimer
      1. 7.5.1 DMTimer Electrical Data and Timing
        1. Table 7-4 DMTimer Timing Conditions
        2. Table 7-5 Timing Requirements for DMTimer [1-7]
        3. Table 7-6 Switching Characteristics for DMTimer [4-7]
    6. 7.6  Ethernet Media Access Controller (EMAC) and Switch
      1. 7.6.1 EMAC and Switch Electrical Data and Timing
        1. Table 7-7 EMAC and Switch Timing Conditions
        2. 7.6.1.1   EMAC/Switch MDIO Electrical Data and Timing
          1. Table 7-8  Timing Requirements for MDIO_DATA
          2. Table 7-9  Switching Characteristics for MDIO_CLK
          3. Table 7-10 Switching Characteristics for MDIO_DATA
        3. 7.6.1.2   EMAC and Switch MII Electrical Data and Timing
          1. Table 7-11 Timing Requirements for GMII[x]_RXCLK - MII Mode
          2. Table 7-12 Timing Requirements for GMII[x]_TXCLK - MII Mode
          3. Table 7-13 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
          4. Table 7-14 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
        4. 7.6.1.3   EMAC and Switch RMII Electrical Data and Timing
          1. Table 7-15 Timing Requirements for RMII[x]_REFCLK - RMII Mode
          2. Table 7-16 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
          3. Table 7-17 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
        5. 7.6.1.4   EMAC and Switch RGMII Electrical Data and Timing
          1. Table 7-18 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
          2. Table 7-19 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
          3. Table 7-20 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
          4. Table 7-21 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
    7. 7.7  External Memory Interfaces
      1. 7.7.1 General-Purpose Memory Controller (GPMC)
        1. 7.7.1.1 GPMC and NOR Flash—Synchronous Mode
          1. Table 7-22 GPMC and NOR Flash Timing Conditions—Synchronous Mode
          2. Table 7-23 GPMC and NOR Flash Timing Requirements—Synchronous Mode
          3. Table 7-24 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
        2. 7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
          1. Table 7-25 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
          2. Table 7-26 GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-27 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
          4. Table 7-28 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        3. 7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
          1. Table 7-29 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
          2. Table 7-30 GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-31 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
          4. Table 7-32 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
      2. 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
        1. 7.7.2.1 mDDR (LPDDR) Routing Guidelines
          1. 7.7.2.1.1 Board Designs
          2. 7.7.2.1.2 LPDDR Interface
            1. 7.7.2.1.2.1 LPDDR Interface Schematic
            2. 7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
              1. Table 7-34 Compatible JEDEC LPDDR Devices (Per Interface)
            3. 7.7.2.1.2.3 PCB Stackup
            4. 7.7.2.1.2.4 Placement
            5. 7.7.2.1.2.5 LPDDR Keepout Region
            6. 7.7.2.1.2.6 Bulk Bypass Capacitors
            7. 7.7.2.1.2.7 High-Speed Bypass Capacitors
            8. 7.7.2.1.2.8 Net Classes
            9. 7.7.2.1.2.9 LPDDR Signal Termination
          3. 7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
        2. 7.7.2.2 DDR2 Routing Guidelines
          1. 7.7.2.2.1 Board Designs
          2. 7.7.2.2.2 DDR2 Interface
            1. 7.7.2.2.2.1  DDR2 Interface Schematic
            2. 7.7.2.2.2.2  Compatible JEDEC DDR2 Devices
              1. Table 7-46 Compatible JEDEC DDR2 Devices (Per Interface)
            3. 7.7.2.2.2.3  PCB Stackup
            4. 7.7.2.2.2.4  Placement
            5. 7.7.2.2.2.5  DDR2 Keepout Region
            6. 7.7.2.2.2.6  Bulk Bypass Capacitors
            7. 7.7.2.2.2.7  High-Speed (HS) Bypass Capacitors
            8. 7.7.2.2.2.8  Net Classes
            9. 7.7.2.2.2.9  DDR2 Signal Termination
            10. 7.7.2.2.2.10 DDR_VREF Routing
          3. 7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
        3. 7.7.2.3 DDR3 and DDR3L Routing Guidelines
          1. 7.7.2.3.1 Board Designs
            1. 7.7.2.3.1.1 DDR3 versus DDR2
          2. 7.7.2.3.2 DDR3 Device Combinations
          3. 7.7.2.3.3 DDR3 Interface
            1. 7.7.2.3.3.1  DDR3 Interface Schematic
            2. 7.7.2.3.3.2  Compatible JEDEC DDR3 Devices
            3. 7.7.2.3.3.3  PCB Stackup
            4. 7.7.2.3.3.4  Placement
            5. 7.7.2.3.3.5  DDR3 Keepout Region
            6. 7.7.2.3.3.6  Bulk Bypass Capacitors
            7. 7.7.2.3.3.7  High-Speed Bypass Capacitors
              1. 7.7.2.3.3.7.1 Return Current Bypass Capacitors
            8. 7.7.2.3.3.8  Net Classes
            9. 7.7.2.3.3.9  DDR3 Signal Termination
            10. 7.7.2.3.3.10 DDR_VREF Routing
            11. 7.7.2.3.3.11 VTT
          4. 7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
            1. 7.7.2.3.4.1 Two DDR3 Devices
              1. 7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
              2. 7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
            2. 7.7.2.3.4.2 One DDR3 Device
              1. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
              2. 7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
          5. 7.7.2.3.5 Data Topologies and Routing Definition
            1. 7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
            2. 7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
          6. 7.7.2.3.6 Routing Specification
            1. 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
            2. 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
    8. 7.8  I2C
      1. 7.8.1 I2C Electrical Data and Timing
        1. Table 7-70 I2C Timing Conditions – Slave Mode
        2. Table 7-71 Timing Requirements for I2C Input Timings
        3. Table 7-72 Switching Characteristics for I2C Output Timings
    9. 7.9  JTAG Electrical Data and Timing
      1. Table 7-73 JTAG Timing Conditions
      2. Table 7-74 Timing Requirements for JTAG
      3. Table 7-75 Switching Characteristics for JTAG
    10. 7.10 LCD Controller (LCDC)
    11. 7.11 Multichannel Audio Serial Port (McASP)
      1. 7.11.1 McASP Device-Specific Information
      2. 7.11.2 McASP Electrical Data and Timing
        1. Table 7-76 McASP Timing Conditions
        2. Table 7-77 Timing Requirements for McASP
        3. Table 7-78 Switching Characteristics for McASP
    12. 7.12 Multichannel Serial Port Interface (McSPI)
      1. 7.12.1 McSPI Electrical Data and Timing
        1. 7.12.1.1 McSPI—Slave Mode
          1. Table 7-79 McSPI Timing Conditions – Slave Mode
          2. Table 7-80 Timing Requirements for McSPI Input Timings—Slave Mode
          3. Table 7-81 Switching Characteristics for McSPI Output Timings—Slave Mode
        2. 7.12.1.2 McSPI—Master Mode
          1. Table 7-82 McSPI Timing Conditions – Master Mode
          2. Table 7-83 Timing Requirements for McSPI Input Timings – Master Mode
          3. Table 7-84 Switching Characteristics for McSPI Output Timings – Master Mode
    13. 7.13 Multimedia Card (MMC) Interface
      1. 7.13.1 MMC Electrical Data and Timing
        1. Table 7-85 MMC Timing Conditions
        2. Table 7-86 Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
        3. Table 7-87 Switching Characteristics for MMC[x]_CLK
        4. Table 7-88 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
        5. Table 7-89 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
    14. 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. Table 7-90 PRU-ICSS PRU Timing Conditions
        2. 7.14.1.1   PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-91 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-92 PRU-ICSS PRU Switching Requirements – Direct Output Mode
        3. 7.14.1.2   PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-93 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        4. 7.14.1.3   PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-94 PRU-ICSS PRU Timing Requirements – Shift In Mode
          2. Table 7-95 PRU-ICSS PRU Switching Requirements - Shift Out Mode
      2. 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. Table 7-96 PRU-ICSS ECAT Timing Conditions
        2. 7.14.2.1   PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-97  PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
          2. Table 7-98  PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
          3. Table 7-99  PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
          4. Table 7-100 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-101 PRU-ICSS ECAT Switching Requirements - Digital I/Os
      3. 7.14.3 PRU-ICSS MII_RT and Switch
        1. Table 7-102 PRU-ICSS MII_RT Switch Timing Conditions
        2. 7.14.3.1    PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-103 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
          2. Table 7-104 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-105 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
        3. 7.14.3.2    PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-106 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
          2. Table 7-107 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-108 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-109 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-110 UART Timing Conditions
        2. Table 7-111 Timing Requirements for PRU-ICSS UART Receive
        3. Table 7-112 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. 7.15.1 UART Electrical Data and Timing
        1. Table 7-113 UART Timing Conditions
        2. Table 7-114 Timing Requirements for UARTx Receive
        3. Table 7-115 Switching Characteristics for UARTx Transmit
      2. 7.15.2 UART IrDA Interface
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Via Channel
    2. 9.2 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZCZ|324
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.3.1 External Memory Interfaces

Table 4-8 External Memory Interfaces/DDR Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCZ BALL [4]
ddr_a0 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O F3
ddr_a1 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O H1
ddr_a10 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O F4
ddr_a11 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O F2
ddr_a12 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O E3
ddr_a13 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O H3
ddr_a14 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O H4
ddr_a15 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O D3
ddr_a2 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O E4
ddr_a3 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O C3
ddr_a4 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O C2
ddr_a5 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O B1
ddr_a6 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O D5
ddr_a7 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O E2
ddr_a8 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O D4
ddr_a9 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O C1
ddr_ba0 DDR SDRAM BANK ADDRESS OUTPUT O C4
ddr_ba1 DDR SDRAM BANK ADDRESS OUTPUT O E1
ddr_ba2 DDR SDRAM BANK ADDRESS OUTPUT O B3
ddr_casn DDR SDRAM COLUMN ADDRESS STROBE OUTPUT (ACTIVE LOW) O F1
ddr_ck DDR SDRAM CLOCK OUTPUT (Differential+) O D2
ddr_cke DDR SDRAM CLOCK ENABLE OUTPUT O G3
ddr_csn0 DDR SDRAM CHIP SELECT OUTPUT O H2
ddr_d0 DDR SDRAM DATA INPUT/OUTPUT I/O M3
ddr_d1 DDR SDRAM DATA INPUT/OUTPUT I/O M4
ddr_d10 DDR SDRAM DATA INPUT/OUTPUT I/O K2
ddr_d11 DDR SDRAM DATA INPUT/OUTPUT I/O K3
ddr_d12 DDR SDRAM DATA INPUT/OUTPUT I/O K4
ddr_d13 DDR SDRAM DATA INPUT/OUTPUT I/O L3
ddr_d14 DDR SDRAM DATA INPUT/OUTPUT I/O L4
ddr_d15 DDR SDRAM DATA INPUT/OUTPUT I/O M1
ddr_d2 DDR SDRAM DATA INPUT/OUTPUT I/O N1
ddr_d3 DDR SDRAM DATA INPUT/OUTPUT I/O N2
ddr_d4 DDR SDRAM DATA INPUT/OUTPUT I/O N3
ddr_d5 DDR SDRAM DATA INPUT/OUTPUT I/O N4
ddr_d6 DDR SDRAM DATA INPUT/OUTPUT I/O P3
ddr_d7 DDR SDRAM DATA INPUT/OUTPUT I/O P4
ddr_d8 DDR SDRAM DATA INPUT/OUTPUT I/O J1
ddr_d9 DDR SDRAM DATA INPUT/OUTPUT I/O K1
ddr_dqm0 DDR WRITE ENABLE / DATA MASK FOR DATA[7:0] O M2
ddr_dqm1 DDR WRITE ENABLE / DATA MASK FOR DATA[15:8] O J2
ddr_dqs0 DDR DATA STROBE FOR DATA[7:0] (Differential+) I/O P1
ddr_dqs1 DDR DATA STROBE FOR DATA[15:8] (Differential+) I/O L1
ddr_dqsn0 DDR DATA STROBE FOR DATA[7:0] (Differential-) I/O P2
ddr_dqsn1 DDR DATA STROBE FOR DATA[15:8] (Differential-) I/O L2
ddr_nck DDR SDRAM CLOCK OUTPUT (Differential-) O D1
ddr_odt ODT OUTPUT O G1
ddr_rasn DDR SDRAM ROW ADDRESS STROBE OUTPUT (ACTIVE LOW) O G4
ddr_resetn DDR3/DDR3L RESET OUTPUT (ACTIVE LOW) O G2
ddr_vref Voltage Reference Input A J4
ddr_vtp VTP Compensation Resistor I J3
ddr_wen DDR SDRAM WRITE ENABLE OUTPUT (ACTIVE LOW) O B2

Table 4-9 External Memory Interfaces/General Purpose Memory Controller Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCZ BALL [4]
gpmc_a0 GPMC Address O R1, R13
gpmc_a1 GPMC Address O R2, U5, V14
gpmc_a10 GPMC Address O T16, V5
gpmc_a11 GPMC Address O R6, V17
gpmc_a12 GPMC Address O U1
gpmc_a13 GPMC Address O U2
gpmc_a14 GPMC Address O U3
gpmc_a15 GPMC Address O U4
gpmc_a16 GPMC Address O R13, V2
gpmc_a17 GPMC Address O V14, V3
gpmc_a18 GPMC Address O U14, V4
gpmc_a19 GPMC Address O T14, T5
gpmc_a2 GPMC Address O R3, R5, U14
gpmc_a20 GPMC Address O F17, R14
gpmc_a21 GPMC Address O F18, V15
gpmc_a22 GPMC Address O G15, U15
gpmc_a23 GPMC Address O G16, T15
gpmc_a24 GPMC Address O G17, V16
gpmc_a25 GPMC Address O G18, U16
gpmc_a26 GPMC Address O T16
gpmc_a27 GPMC Address O V17
gpmc_a3 GPMC Address O R4, T13, T14
gpmc_a4 GPMC Address O R14, T1
gpmc_a5 GPMC Address O T2, V15
gpmc_a6 GPMC Address O T3, U15
gpmc_a7 GPMC Address O T15, T4
gpmc_a8 GPMC Address O U5, V16
gpmc_a9 GPMC Address O R5, U16
gpmc_ad0 GPMC Address and Data I/O U7
gpmc_ad1 GPMC Address and Data I/O V7
gpmc_ad10 GPMC Address and Data I/O T11
gpmc_ad11 GPMC Address and Data I/O U12
gpmc_ad12 GPMC Address and Data I/O T12
gpmc_ad13 GPMC Address and Data I/O R12
gpmc_ad14 GPMC Address and Data I/O V13
gpmc_ad15 GPMC Address and Data I/O U13
gpmc_ad2 GPMC Address and Data I/O R8
gpmc_ad3 GPMC Address and Data I/O T8
gpmc_ad4 GPMC Address and Data I/O U8
gpmc_ad5 GPMC Address and Data I/O V8
gpmc_ad6 GPMC Address and Data I/O R9
gpmc_ad7 GPMC Address and Data I/O T9
gpmc_ad8 GPMC Address and Data I/O U10
gpmc_ad9 GPMC Address and Data I/O T10
gpmc_advn_ale GPMC Address Valid / Address Latch Enable O R7
gpmc_be0n_cle GPMC Byte Enable 0 / Command Latch Enable O T6
gpmc_be1n GPMC Byte Enable 1 O U18, V9
gpmc_clk GPMC Clock I/O U9, V12
gpmc_csn0 GPMC Chip Select O V6
gpmc_csn1 GPMC Chip Select O U9
gpmc_csn2 GPMC Chip Select O V9
gpmc_csn3 GPMC Chip Select O T13
gpmc_csn4 GPMC Chip Select O T17
gpmc_csn5 GPMC Chip Select O U17
gpmc_csn6 GPMC Chip Select O U18
gpmc_dir GPMC Data Direction O U18
gpmc_oen_ren GPMC Output / Read Enable O T7
gpmc_wait0 GPMC Wait 0 I T17
gpmc_wait1 GPMC Wait 1 I V12
gpmc_wen GPMC Write Enable O U6
gpmc_wpn GPMC Write Protect O U17
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