ZHCSHP8B December   2017  – January 2019 AMIC120

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. Table 4-1 ZDN Ball Map [Section Top Left - Top View]
      2. Table 4-2 ZDN Ball Map [Section Top Middle - Top View]
      3. Table 4-3 ZDN Ball Map [Section Top Right - Top View]
      4. Table 4-4 ZDN Ball Map [Section Middle Left - Top View]
      5. Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]
      6. Table 4-6 ZDN Ball Map [Section Middle Right - Top View]
      7. Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]
      8. Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]
      9. Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC Interfaces
      2. 4.3.2  CAN Interfaces
      3. 4.3.3  Debug Subsystem Interface
      4. 4.3.4  Ethernet (GEMAC_CPSW) Interfaces
      5. 4.3.5  External Memory Interfaces
      6. 4.3.6  General Purpose IOs
      7. 4.3.7  HDQ Interface
      8. 4.3.8  I2C Interfaces
      9. 4.3.9  McASP Interfaces
      10. 4.3.10 Miscellaneous
      11. 4.3.11 PRU-ICSS0 Interface
      12. 4.3.12 PRU-ICSS1 Interface
      13. 4.3.13 QSPI Interface
      14. 4.3.14 RTC Subsystem Interface
      15. 4.3.15 Removable Media Interfaces
      16. 4.3.16 SPI Interfaces
      17. 4.3.17 Timer Interfaces
      18. 4.3.18 UART Interfaces
      19. 4.3.19 USB Interfaces
      20. 4.3.20 eCAP Interfaces
      21. 4.3.21 eHRPWM Interfaces
      22. 4.3.22 eQEP Interfaces
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  ADC0: Analog-to-Digital Subsystem Electrical Parameters
    9. 5.9  Thermal Resistance Characteristics
      1. Table 5-6 Thermal Resistance Characteristics (NFBGA Package) [ZDN]
    10. 5.10 External Capacitors
      1. 5.10.1 Voltage Decoupling Capacitors
        1. 5.10.1.1 Core Voltage Decoupling Capacitors
        2. 5.10.1.2 IO and Analog Voltage Decoupling Capacitors
      2. 5.10.2 Output Capacitors
    11. 5.11 Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. 5.11.1.1 Power Supply Slew Rate Requirement
        2. 5.11.1.2 Power-Up Sequencing
        3. 5.11.1.3 Power-Down Sequencing
      2. 5.11.2  Clock
        1. 5.11.2.1 PLLs
          1. 5.11.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
        2. 5.11.2.2 Input Clock Specifications
        3. 5.11.2.3 Input Clock Requirements
          1. 5.11.2.3.1 OSC0 Internal Oscillator Clock Source
            1. Table 5-11 OSC0 Crystal Circuit Requirements
            2. Table 5-12 OSC0 Crystal Circuit Characteristics
          2. 5.11.2.3.2 OSC0 LVCMOS Digital Clock Source
          3. 5.11.2.3.3 OSC1 Internal Oscillator Clock Source
            1. Table 5-14 OSC1 Crystal Circuit Requirements
            2. Table 5-15 OSC1 Crystal Circuit Characteristics
          4. 5.11.2.3.4 OSC1 LVCMOS Digital Clock Source
          5. 5.11.2.3.5 OSC1 Not Used
        4. 5.11.2.4 Output Clock Specifications
        5. 5.11.2.5 Output Clock Characteristics
          1. 5.11.2.5.1 CLKOUT1
          2. 5.11.2.5.2 CLKOUT2
      3. 5.11.3  Timing Parameters and Board Routing Analysis
      4. 5.11.4  Recommended Clock and Control Signal Transition Behavior
      5. 5.11.5  Controller Area Network (CAN)
        1. 5.11.5.1 DCAN Electrical Data and Timing
          1. Table 5-17 Timing Requirements for DCANx Receive
          2. Table 5-18 Switching Characteristics for DCANx Transmit
      6. 5.11.6  DMTimer
        1. 5.11.6.1 DMTimer Electrical Data and Timing
          1. Table 5-19 Timing Requirements for DMTimer [1-11]
          2. Table 5-20 Switching Characteristics for DMTimer [4-7]
      7. 5.11.7  Ethernet Media Access Controller (EMAC) and Switch
        1. 5.11.7.1 Ethernet MAC and Switch Electrical Data and Timing
          1. Table 5-21 Ethernet MAC and Switch Timing Conditions
          2. 5.11.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
            1. Table 5-22 Timing Requirements for MDIO_DATA
            2. Table 5-23 Switching Characteristics for MDIO_CLK
            3. Table 5-24 MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
            1. Table 5-25 Timing Requirements for GMII[x]_RXCLK - MII Mode
            2. Table 5-26 Timing Requirements for GMII[x]_TXCLK - MII Mode
            3. Table 5-27 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
            4. Table 5-28 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
          4. 5.11.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
            1. Table 5-29 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-30 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-31 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          5. 5.11.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
            1. Table 5-32 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-33 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-34 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-35 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
      8. 5.11.8  External Memory Interfaces
        1. 5.11.8.1 General-Purpose Memory Controller (GPMC)
          1. 5.11.8.1.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-36 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-37 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-38 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.11.8.1.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-39 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
            2. Table 5-40 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-41 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            4. Table 5-42 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.11.8.1.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-43 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
            2. Table 5-44 GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-45 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            4. Table 5-46 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        2. 5.11.8.2 Memory Interface
          1. 5.11.8.2.1 DDR3 and DDR3L Routing Guidelines
            1. 5.11.8.2.1.1 Board Designs
            2. 5.11.8.2.1.2 DDR3 Device Combinations
            3. 5.11.8.2.1.3 DDR3 Interface
              1. 5.11.8.2.1.3.1  DDR3 Interface Schematic
              2. 5.11.8.2.1.3.2  Compatible JEDEC DDR3 Devices
              3. 5.11.8.2.1.3.3  DDR3 PCB Stackup
              4. 5.11.8.2.1.3.4  DDR3 Placement
              5. 5.11.8.2.1.3.5  DDR3 Keepout Region
              6. 5.11.8.2.1.3.6  DDR3 Bulk Bypass Capacitors
              7. 5.11.8.2.1.3.7  DDR3 High-Speed Bypass Capacitors
                1. 5.11.8.2.1.3.7.1 Return Current Bypass Capacitors
              8. 5.11.8.2.1.3.8  DDR3 Net Classes
              9. 5.11.8.2.1.3.9  DDR3 Signal Termination
              10. 5.11.8.2.1.3.10 DDR3 DDR_VREF Routing
              11. 5.11.8.2.1.3.11 DDR3 VTT
            4. 5.11.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
              1. 5.11.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
                1. 5.11.8.2.1.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 5.11.8.2.1.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              2. 5.11.8.2.1.4.2 Using Four 8-Bit DDR3 Devices
                1. 5.11.8.2.1.4.2.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 5.11.8.2.1.4.2.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              3. 5.11.8.2.1.4.3 One 16-Bit DDR3 Device
                1. 5.11.8.2.1.4.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 5.11.8.2.1.4.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
            5. 5.11.8.2.1.5 Data Topologies and Routing Definition
              1. 5.11.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
              2. 5.11.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
            6. 5.11.8.2.1.6 Routing Specification
              1. 5.11.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
              2. 5.11.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
          2. 5.11.8.2.2 LPDDR2 Routing Guidelines
            1. 5.11.8.2.2.1 LPDDR2 Board Designs
            2. 5.11.8.2.2.2 LPDDR2 Device Configurations
            3. 5.11.8.2.2.3 LPDDR2 Interface
              1. 5.11.8.2.2.3.1 LPDDR2 Interface Schematic
              2. 5.11.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
              3. 5.11.8.2.2.3.3 LPDDR2 PCB Stackup
              4. 5.11.8.2.2.3.4 LPDDR2 Placement
              5. 5.11.8.2.2.3.5 LPDDR2 Keepout Region
              6. 5.11.8.2.2.3.6 LPDDR2 Net Classes
              7. 5.11.8.2.2.3.7 LPDDR2 Signal Termination
              8. 5.11.8.2.2.3.8 LPDDR2 DDR_VREF Routing
            4. 5.11.8.2.2.4 Routing Specification
              1. 5.11.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
              2. 5.11.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
      9. 5.11.9  Display Subsystem (DSS)
      10. 5.11.10 Camera (VPFE)
      11. 5.11.11 Inter-Integrated Circuit (I2C)
        1. 5.11.11.1 I2C Electrical Data and Timing
          1. Table 5-69 I2C Timing Conditions - Slave Mode
          2. Table 5-70 Timing Requirements for I2C Input Timings
          3. Table 5-71 Switching Characteristics for I2C Output Timings
      12. 5.11.12 Multichannel Audio Serial Port (McASP)
        1. 5.11.12.1 McASP Device-Specific Information
        2. 5.11.12.2 McASP Electrical Data and Timing
          1. Table 5-72 McASP Timing Conditions
          2. Table 5-73 Timing Requirements for McASP
          3. Table 5-74 Switching Characteristics for McASP
      13. 5.11.13 Multichannel Serial Port Interface (McSPI)
        1. 5.11.13.1 McSPI Electrical Data and Timing
          1. 5.11.13.1.1 McSPI—Slave Mode
            1. Table 5-75 McSPI Timing Conditions—Slave Mode
            2. Table 5-76 Timing Requirements for McSPI Input Timings—Slave Mode
            3. Table 5-77 Switching Characteristics for McSPI Output Timings—Slave Mode
          2. 5.11.13.1.2 McSPI—Master Mode
            1. Table 5-78 McSPI Timing Conditions—Master Mode
            2. Table 5-79 Timing Requirements for McSPI Input Timings—Master Mode
            3. Table 5-80 Switching Characteristics for McSPI Output Timings—Master Mode
      14. 5.11.14 Quad Serial Port Interface (QSPI)
        1. Table 5-81 QSPI Switching Characteristics
      15. 5.11.15 HDQ/1-Wire Interface (HDQ/1-Wire)
        1. 5.11.15.1 HDQ Protocol
        2. 5.11.15.2 1-Wire Protocol
      16. 5.11.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
        1. 5.11.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
          1. Table 5-86  PRU-ICSS PRU Timing Conditions
          2. 5.11.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            1. Table 5-87 PRU-ICSS PRU Timing Requirements - Direct Input Mode
            2. Table 5-88 PRU-ICSS PRU Switching Requirements - Direct Output Mode
          3. 5.11.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            1. Table 5-89 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
          4. 5.11.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
            1. Table 5-90 PRU-ICSS PRU Timing Requirements - Shift In Mode
            2. Table 5-91 PRU-ICSS PRU Switching Requirements - Shift Out Mode
          5. 5.11.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
            1. Table 5-92 PRU-ICSS Timing Requirements - Sigma Delta Mode
          6. 5.11.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
            1. Table 5-93 PRU-ICSS Timing Requirements - ENDAT Mode
            2. Table 5-94 PRU-ICSS Switching Requirements - ENDAT Mode
        2. 5.11.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
          1. Table 5-95  PRU-ICSS ECAT Timing Conditions
          2. 5.11.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
            1. Table 5-96  PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
            2. Table 5-97  PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
            3. Table 5-98  PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
            4. Table 5-99  PRU-ICSS ECAT Timing Requirements - LATCHx_IN
            5. Table 5-100 PRU-ICSS ECAT Switching Requirements - Digital IOs
        3. 5.11.16.3 PRU-ICSS MII_RT and Switch
          1. Table 5-101 PRU-ICSS MII_RT Switch Timing Conditions
          2. 5.11.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
            1. Table 5-102 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
            2. Table 5-103 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
            3. Table 5-104 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
            1. Table 5-105 PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
            2. Table 5-106 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
            3. Table 5-107 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
            4. Table 5-108 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
        4. 5.11.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          1. Table 5-109 Timing Requirements for PRU-ICSS UART Receive
          2. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      17. 5.11.17 Multimedia Card (MMC) Interface
        1. 5.11.17.1 MMC Electrical Data and Timing
          1. Table 5-111 MMC Timing Conditions
          2. Table 5-112 Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
          3. Table 5-113 Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
          4. Table 5-114 Switching Characteristics for MMC[x]_CLK
          5. Table 5-115 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
          6. Table 5-116 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
      18. 5.11.18 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.11.18.1 UART Electrical Data and Timing
          1. Table 5-117 Timing Requirements for UARTx Receive
          2. Table 5-118 for UARTx Transmit
        2. 5.11.18.2 UART IrDA Interface
    12. 5.12 Emulation and Debug
      1. 5.12.1 IEEE 1149.1 JTAG
        1. 5.12.1.1 JTAG Electrical Data and Timing
          1. Table 5-121 Timing Requirements for JTAG
          2. Table 5-122 Switching Characteristics for JTAG
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Community Resources
    5. 6.5 商标
    6. 6.6 静电放电警告
    7. 6.7 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Via Channel
    2. 7.2 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZDN|491
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.1 Pin Diagrams

NOTE

The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package.

CAUTION

Not all exposed peripherals are supported on the AMIC120 device. Refer to Table 3-1, Device Comparison Table, for details on supported peripherals.

Table 4-1 ZDN Ball Map [Section Top Left - Top View]

A B C D E F G H
25 VSS XTALOUT XTALIN gpio5_8 gpio5_12 USB1_DRVVBUS EXTINTn uart3_rxd
24 dss_ac_bias_en VSS_OSC xdma_event_intr1 xdma_event_intr0 gpio5_13 gpio5_9 eCAP0_in_PWM0_out uart3_txd
23 dss_hsync dss_vsync VDDS_OSC VDDS_CLKOUT gpio5_11 mcasp0_axr0
22 dss_pclk dss_data0 VDDSHV5 WARMRSTn uart3_ctsn
21 dss_data1 dss_data2 dss_data3 USB0_DRVVBUS Reserved
20 dss_data4 dss_data5 dss_data6 vdd_mpu_mon VDDS gpio5_10 clkreq
19 dss_data8 dss_data9 dss_data12 dss_data13 dss_data7 CAP_VBB_MPU Reserved
18 dss_data10 dss_data11 VSS

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-2 ZDN Ball Map [Section Top Middle - Top View]

J K L M N P R T
25 uart0_rtsn uart0_rxd uart0_ctsn mcasp0_axr1 spi4_cs0 spi4_sclk spi0_cs1 USB1_VBUS
24 uart0_txd uart3_rtsn mcasp0_ahclkx mcasp0_ahclkr mcasp0_aclkx spi4_d1 spi4_d0 EMU1
23 mcasp0_fsr mcasp0_aclkr EMU0 spi0_sclk spi2_cs0
22 uart1_ctsn uart1_rtsn mcasp0_fsx spi2_d0 spi0_d0
21 uart1_rxd uart1_txd VDDS_PLL_CORE_LCD VPP spi0_d1
20 VDD_MPU VDD_MPU spi2_sclk spi2_d1 spi0_cs0
19 VDD_MPU VDD_MPU VDDSHV3 VDDS VDD_CORE
18 VDDSHV3 VDDSHV3 VSS VDD_MPU VDDSHV3 VDDSHV3 VSS VDD_CORE

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-3 ZDN Ball Map [Section Top Right - Top View]

U V W Y AA AB AC AD AE
25 USB1_ID USB1_DM USB0_DP nTRST TCK cam1_wen cam1_field cam1_hd VSS
24 USB0_ID USB1_DP USB0_DM TMS TDO I2C0_SDA cam1_data9 cam1_data8 cam1_data7
23 USB0_VBUS VSSA_USB PWRONRSTn VSS cam1_vd cam1_data6 cam1_data5
22 USB1_CE USB0_CE I2C0_SCL cam1_data4 cam1_data3
21 VDDA1P8V_USB1 VDDA1P8V_USB0 cam1_data1 cam1_data2 cam1_pclk
20 VDDA3P3V_USB1 VDDA3P3V_USB0 TDI cam1_data0 cam0_pclk cam0_data7 cam0_data6
19 VSS VDDS cam0_data9 cam0_data8 cam0_data5 cam0_data4
18 VSS VSS VDDSHV3 cam0_data2 cam0_data3 cam0_data1 cam0_field cam0_vd cam0_data0

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-4 ZDN Ball Map [Section Middle Left - Top View]

A B C D E F G H
17 mdio_data mdio_clk dss_data14 dss_data15 VDDS_PLL_MPU mii1_rxd0 VDDSHV6 VDDSHV6
16 rmii1_ref_clk mii1_rxd1 mii1_txd3 mii1_col mii1_rxd2 VDDSHV7 VDDSHV6 VDD_MPU
15 mii1_rx_dv mii1_txd0 VSS
14 mii1_txd1 mii1_crs mii1_rxd3 mii1_tx_clk CAP_VDD_SRAM_MPU VDDS_SRAM_MPU_BB VDDSHV8 VDD_MPU
13 mii1_tx_en mii1_rx_er mii1_txd2 mii1_rx_clk CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDSHV8 VDD_MPU
12 gpmc_clk gpmc_csn3 VDDS
11 gpmc_ad15 gpmc_ad14 gpmc_ad13 gpmc_ad11 gpmc_ad12 gpmc_ad10 VDDSHV9 VDDSHV9
10 gpmc_ad9 gpmc_ad8 gpmc_be0n_cle gpmc_wen gpmc_oen_ren gpmc_csn2 VDDSHV10 VDDSHV10

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]

J K L M N P R T
17 VSS VDDSHV3 VSS VDD_MPU VDD_CORE VDD_CORE VSS VSS
16 VDD_MPU VSS VDD_CORE VDD_CORE
15 VSS VSS VSS VSS VSS VSS VSS VSS
14 VDD_MPU VSS VDD_CORE VDD_CORE VSS VSS VDD_CORE VDD_CORE
13 VDD_MPU VSS VSS VSS
12 VSS VSS VDD_CORE VDD_CORE VSS VSS VSS VSS
11 VDD_CORE VSS VSS VSS VSS VSS VDD_CORE VDD_CORE
10 VDD_CORE VSS VSS VSS

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-6 ZDN Ball Map [Section Middle Right - Top View]

U V W Y AA AB AC AD AE
17 VSS VDDSHV2 cam0_wen cam0_hd
16 VSS VDDSHV2 VDDSHV2 VDDA_ADC1 ADC1_AIN2 ADC1_AIN1 ADC1_AIN0 ADC1_AIN7 ADC1_AIN6
15 VDD_CORE VDD_CORE VDDS ADC1_AIN5 ADC1_AIN4 ADC1_AIN3 VSSA_ADC ADC1_VREFN ADC1_VREFP
14 VSS VSS ADC0_VREFP ADC0_VREFN
13 VSS VSS VDD_CORE ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 ADC0_AIN5 ADC0_AIN6 ADC0_AIN7
12 VSS VSS VDD_CORE ADC0_AIN1 ADC0_AIN0 VDDA_ADC0 Reserved VDDS Reserved
11 VSS VSS Reserved Reserved
10 VSS VSS Reserved Reserved Reserved Reserved Reserved Reserved VSS

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]

A B C D E F G H
9 gpmc_advn_ale gpmc_csn1 VDDSHV11
8 gpmc_csn0 gpmc_ad7 gpmc_ad6 gpmc_a11 gpmc_a6 VDDS3P3V_IOLDO gpmc_a10 VDDSHV11
7 gpmc_ad5 gpmc_ad4 gpmc_a4 gpmc_a5 gpmc_a8
6 gpmc_ad3 gpmc_ad2 gpmc_a2 CAP_VDDS1P8V_IOLDO gpmc_a7 VDDS
5 gpmc_ad1 gpmc_ad0 gpmc_a1 VDDS_PLL_DDR
4 gpmc_a3 gpmc_a9 ddr_dqm0 ddr_d4
3 gpmc_be1n gpmc_wpn gpmc_a0 ddr_d0 ddr_d3 ddr_d5
2 gpmc_wait0 mmc0_dat2 mmc0_dat1 mmc0_cmd ddr_d1 ddr_dqs0 ddr_d6 ddr_dqm1
1 VSS mmc0_dat3 mmc0_dat0 mmc0_clk ddr_d2 ddr_dqsn0 ddr_d7 ddr_d8

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]

J K L M N P R T
9 VSS VSS VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
8 VDDSHV1 VDDS_DDR VSS VDDS_DDR VDDS_DDR VSS VDDS_DDR VDDS_DDR
7 VDDSHV1 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR
6 ddr_d9 ddr_d13 ddr_a10 ddr_cke1 VDDS_DDR ddr_vref
5 ddr_d10 ddr_d14 ddr_csn0 ddr_a13 ddr_a5 ddr_a11
4 ddr_d11 ddr_d15 ddr_csn1 ddr_wen ddr_a6 ddr_a12
3 ddr_d12 ddr_ba2 ddr_cke0 ddr_casn ddr_a7 ddr_a14
2 ddr_dqs1 ddr_ba1 ddr_a2 ddr_ck ddr_rasn ddr_a3 ddr_a8 ddr_a15
1 ddr_dqsn1 ddr_ba0 ddr_a1 ddr_nck ddr_a0 ddr_a4 ddr_a9 ddr_resetn

Ball Map Position

1 2 3
4 5 6
7 8 9

Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]

U V W Y AA AB AC AD AE
9 VSS VSS Reserved Reserved Reserved VDD_CORE Reserved
8 VSS VDDS_DDR VDDS VSS
7 VDDS_DDR Reserved Reserved Reserved Reserved Reserved VSS
6 ddr_dqm2 ddr_d23 Reserved Reserved Reserved RTC_PMIC_EN RTC_PWRONRSTn
5 ddr_d16 ddr_d22 Reserved VDDS_RTC RTC_XTALIN
4 ddr_d17 ddr_d21 ddr_d26 VSS_RTC RTC_XTALOUT
3 ddr_d18 ddr_d25 ddr_d27 ddr_vtp CAP_VDD_RTC RTC_WAKEUP
2 ddr_odt1 ddr_d19 ddr_dqsn2 ddr_d24 ddr_dqsn3 ddr_d28 ddr_d31 Reserved RTC_KALDO_ENn
1 ddr_odt0 ddr_d20 ddr_dqs2 ddr_dqm3 ddr_dqs3 ddr_d29 ddr_d30 Reserved VSS

Ball Map Position

1 2 3
4 5 6
7 8 9
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