ZHCSHP8B December   2017  – January 2019 AMIC120

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. Table 4-1 ZDN Ball Map [Section Top Left - Top View]
      2. Table 4-2 ZDN Ball Map [Section Top Middle - Top View]
      3. Table 4-3 ZDN Ball Map [Section Top Right - Top View]
      4. Table 4-4 ZDN Ball Map [Section Middle Left - Top View]
      5. Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]
      6. Table 4-6 ZDN Ball Map [Section Middle Right - Top View]
      7. Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]
      8. Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]
      9. Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC Interfaces
      2. 4.3.2  CAN Interfaces
      3. 4.3.3  Debug Subsystem Interface
      4. 4.3.4  Ethernet (GEMAC_CPSW) Interfaces
      5. 4.3.5  External Memory Interfaces
      6. 4.3.6  General Purpose IOs
      7. 4.3.7  HDQ Interface
      8. 4.3.8  I2C Interfaces
      9. 4.3.9  McASP Interfaces
      10. 4.3.10 Miscellaneous
      11. 4.3.11 PRU-ICSS0 Interface
      12. 4.3.12 PRU-ICSS1 Interface
      13. 4.3.13 QSPI Interface
      14. 4.3.14 RTC Subsystem Interface
      15. 4.3.15 Removable Media Interfaces
      16. 4.3.16 SPI Interfaces
      17. 4.3.17 Timer Interfaces
      18. 4.3.18 UART Interfaces
      19. 4.3.19 USB Interfaces
      20. 4.3.20 eCAP Interfaces
      21. 4.3.21 eHRPWM Interfaces
      22. 4.3.22 eQEP Interfaces
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  ADC0: Analog-to-Digital Subsystem Electrical Parameters
    9. 5.9  Thermal Resistance Characteristics
      1. Table 5-6 Thermal Resistance Characteristics (NFBGA Package) [ZDN]
    10. 5.10 External Capacitors
      1. 5.10.1 Voltage Decoupling Capacitors
        1. 5.10.1.1 Core Voltage Decoupling Capacitors
        2. 5.10.1.2 IO and Analog Voltage Decoupling Capacitors
      2. 5.10.2 Output Capacitors
    11. 5.11 Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. 5.11.1.1 Power Supply Slew Rate Requirement
        2. 5.11.1.2 Power-Up Sequencing
        3. 5.11.1.3 Power-Down Sequencing
      2. 5.11.2  Clock
        1. 5.11.2.1 PLLs
          1. 5.11.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
        2. 5.11.2.2 Input Clock Specifications
        3. 5.11.2.3 Input Clock Requirements
          1. 5.11.2.3.1 OSC0 Internal Oscillator Clock Source
            1. Table 5-11 OSC0 Crystal Circuit Requirements
            2. Table 5-12 OSC0 Crystal Circuit Characteristics
          2. 5.11.2.3.2 OSC0 LVCMOS Digital Clock Source
          3. 5.11.2.3.3 OSC1 Internal Oscillator Clock Source
            1. Table 5-14 OSC1 Crystal Circuit Requirements
            2. Table 5-15 OSC1 Crystal Circuit Characteristics
          4. 5.11.2.3.4 OSC1 LVCMOS Digital Clock Source
          5. 5.11.2.3.5 OSC1 Not Used
        4. 5.11.2.4 Output Clock Specifications
        5. 5.11.2.5 Output Clock Characteristics
          1. 5.11.2.5.1 CLKOUT1
          2. 5.11.2.5.2 CLKOUT2
      3. 5.11.3  Timing Parameters and Board Routing Analysis
      4. 5.11.4  Recommended Clock and Control Signal Transition Behavior
      5. 5.11.5  Controller Area Network (CAN)
        1. 5.11.5.1 DCAN Electrical Data and Timing
          1. Table 5-17 Timing Requirements for DCANx Receive
          2. Table 5-18 Switching Characteristics for DCANx Transmit
      6. 5.11.6  DMTimer
        1. 5.11.6.1 DMTimer Electrical Data and Timing
          1. Table 5-19 Timing Requirements for DMTimer [1-11]
          2. Table 5-20 Switching Characteristics for DMTimer [4-7]
      7. 5.11.7  Ethernet Media Access Controller (EMAC) and Switch
        1. 5.11.7.1 Ethernet MAC and Switch Electrical Data and Timing
          1. Table 5-21 Ethernet MAC and Switch Timing Conditions
          2. 5.11.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
            1. Table 5-22 Timing Requirements for MDIO_DATA
            2. Table 5-23 Switching Characteristics for MDIO_CLK
            3. Table 5-24 MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
            1. Table 5-25 Timing Requirements for GMII[x]_RXCLK - MII Mode
            2. Table 5-26 Timing Requirements for GMII[x]_TXCLK - MII Mode
            3. Table 5-27 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
            4. Table 5-28 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
          4. 5.11.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
            1. Table 5-29 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-30 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-31 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          5. 5.11.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
            1. Table 5-32 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-33 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-34 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-35 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
      8. 5.11.8  External Memory Interfaces
        1. 5.11.8.1 General-Purpose Memory Controller (GPMC)
          1. 5.11.8.1.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-36 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-37 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-38 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.11.8.1.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-39 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
            2. Table 5-40 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-41 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            4. Table 5-42 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.11.8.1.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-43 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
            2. Table 5-44 GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-45 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            4. Table 5-46 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        2. 5.11.8.2 Memory Interface
          1. 5.11.8.2.1 DDR3 and DDR3L Routing Guidelines
            1. 5.11.8.2.1.1 Board Designs
            2. 5.11.8.2.1.2 DDR3 Device Combinations
            3. 5.11.8.2.1.3 DDR3 Interface
              1. 5.11.8.2.1.3.1  DDR3 Interface Schematic
              2. 5.11.8.2.1.3.2  Compatible JEDEC DDR3 Devices
              3. 5.11.8.2.1.3.3  DDR3 PCB Stackup
              4. 5.11.8.2.1.3.4  DDR3 Placement
              5. 5.11.8.2.1.3.5  DDR3 Keepout Region
              6. 5.11.8.2.1.3.6  DDR3 Bulk Bypass Capacitors
              7. 5.11.8.2.1.3.7  DDR3 High-Speed Bypass Capacitors
                1. 5.11.8.2.1.3.7.1 Return Current Bypass Capacitors
              8. 5.11.8.2.1.3.8  DDR3 Net Classes
              9. 5.11.8.2.1.3.9  DDR3 Signal Termination
              10. 5.11.8.2.1.3.10 DDR3 DDR_VREF Routing
              11. 5.11.8.2.1.3.11 DDR3 VTT
            4. 5.11.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
              1. 5.11.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
                1. 5.11.8.2.1.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 5.11.8.2.1.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              2. 5.11.8.2.1.4.2 Using Four 8-Bit DDR3 Devices
                1. 5.11.8.2.1.4.2.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 5.11.8.2.1.4.2.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              3. 5.11.8.2.1.4.3 One 16-Bit DDR3 Device
                1. 5.11.8.2.1.4.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 5.11.8.2.1.4.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
            5. 5.11.8.2.1.5 Data Topologies and Routing Definition
              1. 5.11.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
              2. 5.11.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
            6. 5.11.8.2.1.6 Routing Specification
              1. 5.11.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
              2. 5.11.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
          2. 5.11.8.2.2 LPDDR2 Routing Guidelines
            1. 5.11.8.2.2.1 LPDDR2 Board Designs
            2. 5.11.8.2.2.2 LPDDR2 Device Configurations
            3. 5.11.8.2.2.3 LPDDR2 Interface
              1. 5.11.8.2.2.3.1 LPDDR2 Interface Schematic
              2. 5.11.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
              3. 5.11.8.2.2.3.3 LPDDR2 PCB Stackup
              4. 5.11.8.2.2.3.4 LPDDR2 Placement
              5. 5.11.8.2.2.3.5 LPDDR2 Keepout Region
              6. 5.11.8.2.2.3.6 LPDDR2 Net Classes
              7. 5.11.8.2.2.3.7 LPDDR2 Signal Termination
              8. 5.11.8.2.2.3.8 LPDDR2 DDR_VREF Routing
            4. 5.11.8.2.2.4 Routing Specification
              1. 5.11.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
              2. 5.11.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
      9. 5.11.9  Display Subsystem (DSS)
      10. 5.11.10 Camera (VPFE)
      11. 5.11.11 Inter-Integrated Circuit (I2C)
        1. 5.11.11.1 I2C Electrical Data and Timing
          1. Table 5-69 I2C Timing Conditions - Slave Mode
          2. Table 5-70 Timing Requirements for I2C Input Timings
          3. Table 5-71 Switching Characteristics for I2C Output Timings
      12. 5.11.12 Multichannel Audio Serial Port (McASP)
        1. 5.11.12.1 McASP Device-Specific Information
        2. 5.11.12.2 McASP Electrical Data and Timing
          1. Table 5-72 McASP Timing Conditions
          2. Table 5-73 Timing Requirements for McASP
          3. Table 5-74 Switching Characteristics for McASP
      13. 5.11.13 Multichannel Serial Port Interface (McSPI)
        1. 5.11.13.1 McSPI Electrical Data and Timing
          1. 5.11.13.1.1 McSPI—Slave Mode
            1. Table 5-75 McSPI Timing Conditions—Slave Mode
            2. Table 5-76 Timing Requirements for McSPI Input Timings—Slave Mode
            3. Table 5-77 Switching Characteristics for McSPI Output Timings—Slave Mode
          2. 5.11.13.1.2 McSPI—Master Mode
            1. Table 5-78 McSPI Timing Conditions—Master Mode
            2. Table 5-79 Timing Requirements for McSPI Input Timings—Master Mode
            3. Table 5-80 Switching Characteristics for McSPI Output Timings—Master Mode
      14. 5.11.14 Quad Serial Port Interface (QSPI)
        1. Table 5-81 QSPI Switching Characteristics
      15. 5.11.15 HDQ/1-Wire Interface (HDQ/1-Wire)
        1. 5.11.15.1 HDQ Protocol
        2. 5.11.15.2 1-Wire Protocol
      16. 5.11.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
        1. 5.11.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
          1. Table 5-86  PRU-ICSS PRU Timing Conditions
          2. 5.11.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            1. Table 5-87 PRU-ICSS PRU Timing Requirements - Direct Input Mode
            2. Table 5-88 PRU-ICSS PRU Switching Requirements - Direct Output Mode
          3. 5.11.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            1. Table 5-89 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
          4. 5.11.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
            1. Table 5-90 PRU-ICSS PRU Timing Requirements - Shift In Mode
            2. Table 5-91 PRU-ICSS PRU Switching Requirements - Shift Out Mode
          5. 5.11.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
            1. Table 5-92 PRU-ICSS Timing Requirements - Sigma Delta Mode
          6. 5.11.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
            1. Table 5-93 PRU-ICSS Timing Requirements - ENDAT Mode
            2. Table 5-94 PRU-ICSS Switching Requirements - ENDAT Mode
        2. 5.11.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
          1. Table 5-95  PRU-ICSS ECAT Timing Conditions
          2. 5.11.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
            1. Table 5-96  PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
            2. Table 5-97  PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
            3. Table 5-98  PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
            4. Table 5-99  PRU-ICSS ECAT Timing Requirements - LATCHx_IN
            5. Table 5-100 PRU-ICSS ECAT Switching Requirements - Digital IOs
        3. 5.11.16.3 PRU-ICSS MII_RT and Switch
          1. Table 5-101 PRU-ICSS MII_RT Switch Timing Conditions
          2. 5.11.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
            1. Table 5-102 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
            2. Table 5-103 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
            3. Table 5-104 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
            1. Table 5-105 PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
            2. Table 5-106 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
            3. Table 5-107 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
            4. Table 5-108 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
        4. 5.11.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          1. Table 5-109 Timing Requirements for PRU-ICSS UART Receive
          2. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      17. 5.11.17 Multimedia Card (MMC) Interface
        1. 5.11.17.1 MMC Electrical Data and Timing
          1. Table 5-111 MMC Timing Conditions
          2. Table 5-112 Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
          3. Table 5-113 Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
          4. Table 5-114 Switching Characteristics for MMC[x]_CLK
          5. Table 5-115 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
          6. Table 5-116 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
      18. 5.11.18 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.11.18.1 UART Electrical Data and Timing
          1. Table 5-117 Timing Requirements for UARTx Receive
          2. Table 5-118 for UARTx Transmit
        2. 5.11.18.2 UART IrDA Interface
    12. 5.12 Emulation and Debug
      1. 5.12.1 IEEE 1149.1 JTAG
        1. 5.12.1.1 JTAG Electrical Data and Timing
          1. Table 5-121 Timing Requirements for JTAG
          2. Table 5-122 Switching Characteristics for JTAG
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Community Resources
    5. 6.5 商标
    6. 6.6 静电放电警告
    7. 6.7 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Via Channel
    2. 7.2 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZDN|491
散热焊盘机械数据 (封装 | 引脚)
订购信息

1.3 说明

TI AMIC120 高性能处理器基于 ARM Cortex-A9 内核。

这些处理器通过协处理器得到增强，该协处理器可进行确定性实时处理（包括 EtherCAT、PROFIBUS、EnDat 等工业通信协议）。该器件支持高级操作系统 (HLOS)。 基于 Linux 的®可从 TI 免费获取。其它 HLOS 可从 TI 的设计网络和生态系统合作伙伴处获取。

这些器件支持对采用较低性能 ARM 内核的系统升级，并提供更新外设，包括 QSPI-NOR 和 LPDDR2 等存储器选项。

这些处理器包含功能方框图中显示的子系统，并且后跟相应的 “说明”中添加了更多信息 说明。

可编程实时单元子系统和工业通信子系统 (PRU-ICSS) 与 ARM 内核分离，允许单独操作和计时，以实现更高的效率和灵活性。PRU-ICSS 支持更多外设接口和 EtherCAT、PROFINET、EtherNet/IP、PROFIBUS、Ethernet Powerlink、Sercos、EnDat 等实时协议。PRU-ICSS 可并行支持 EnDat 和另一个工业通信协议。此外，凭借 PRU-ICSS 的可编程特性及其对引脚、事件和所有片上系统 (SoC) 资源的访问权限，该子系统可以灵活地实现快速实时响应、专用数据处理操作以及定制外设接口，并灵活地减轻 SoC 其他处理器内核的任务负载。

高性能互连为多个初启程序提供到内部和外部存储器控制器以及到片上外设的高带宽数据传送。该器件还提供全面的时钟管理机制。

一个片上模数转换器 (ADC1) 可以与脉宽模块相结合，以创建闭环电机控制解决方案。

实 RTC 提供独立电源域的时钟基准。该时钟基准实现了电池供电的时钟基准。

每个 AMIC120 器件都具有加密加速功能。

器件信息(1)

器件型号 封装 封装尺寸
AMIC120ZDN NFBGA (491) 17.0mm × 17.0mm
(1) 更多信息，请参阅Section 7，机械、封装和可订购米6体育平台手机版_好二三四信息。
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