10.2.3.2 Output Voltage and Logic Input Level

For ATL431LI-Q1 to properly be used as a comparator, the logic output must be readable by the receiving logic device. This is accomplished by knowing the input high and low level threshold voltage levels, typically denoted by V_IH and V_IL.

As seen in Figure 24, the output low level voltage of the ATL431LI-Q1 in open-loop/comparator mode is approximately 2 V, which is typically sufficient for 5 V supplied logic. However, this does not work for 3.3 V and 1.8 V supplied logic. To accommodate this, a resistive divider can be tied to the output to attenuate the output voltage to a voltage legible to the receiving low voltage logic device.

The output high voltage of the ATL431 is equal to V_SUP due to ATL431LI-Q1 being open-collector. If V_SUP is much higher than the maximum input voltage tolerance of the receiving logic, the output must be attenuated to accommodate the reliability of the outgoing logic.

When using a resistive divider on the output, make sure the sum of the resistive divider (R1 and R2 in Figure 23) is much greater than R_SUP to not interfere with the ability of the ATL431LI-Q1 to pull close to V_SUP when turning off.