米6体育平台手机版

ZHCSHS2C may 2017 – january 2022 AWR1443

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

ABL|161

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.3 Pin Multiplexing

Table 7-1 Pin Multiplexing

REGISTER ADDRESS⁽¹⁾	PIN NAME	PIN	DIGITAL PIN MUX CONFIG VALUE [Bits3:0]	FUNCTION			PAD STATE nReset = 0 [ASSERTED]
REGISTER ADDRESS⁽¹⁾	PIN NAME	PIN	DIGITAL PIN MUX CONFIG VALUE [Bits3:0]	SIGNAL NAME	SIGNAL DESCRIPTION	SIGNAL TYPE	STATE	INTERNAL WEAK PULL STATE
EA00h	GPIO_12	P6	0	GPIO_12	General Purpose IO	IO	Hi-Z	Weak Pull Down
EA00h	GPIO_12	P6	1	SPI_HOST1_INTR	General Purpose IO [AWR14xx]	O
EA04h	GPIO_0	N4	0	GPIO_13	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	GPIO_0	General Purpose IO	IO
			2	PMIC_CLKOUT	Dithered Clock Output for PMIC	O
EA08h	GPIO_1	N7	0	GPIO_16	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	GPIO_1	General Purpose IO	IO
			2	SYNC_OUT	Low Frequency Synchronization Signal output	O
EA0Ch	MOSI_1	R8	0	GPIO_19	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	MOSI_1	SPI Channel#1 Data Input	IO
			2	CAN_RX	CAN Interface	I
EA10h	MISO_1	P5	0	GPIO_20	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	MISO_1	SPI Channel#1 Data Output	IO
			2	CAN_TX	CAN Interface	O
EA14h	SPI_CLK_1	R9	0	GPIO_3	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	SPI_CLK_1	SPI Channel#1 Clock	IO
				RCOSC_CLK		O
EA18h	SPI_CS_1	R7	0	GPIO_30	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	SPI_CS_1	SPI Channel#1 Chip Select	IO
				RCOSC_CLK		O
EA1Ch	MOSI_2	R3	0	GPIO_21	General Purpose IO	IO	Hi-Z
			1	MOSI_2	SPI Channel#2 Data Input	IO
			2	I2C_SDA	I2C Data	IO
EA20h	MISO_2	P4	0	GPIO_22	General Purpose IO	IO	Hi-Z
			1	MISO_2	SPI Channel#2 Data Output	IO
			2	I2C_SCL	I2C Clock	IO
EA24h	SPI_CLK_2	R5	0	GPIO_5	General Purpose IO	IO	Hi-Z
			1	SPI_CLK_2	SPI Channel#2 Clock	IO
				MSS_UARTA_RX		IO
			6	MSS_UARTB_TX	Debug: Firmware Trace	O
			7	BSS_UART_TX	Debug: Firmware Trace	O
EA28h	SPI_CS_2	R4	0	GPIO_4	General Purpose IO	IO	Hi-Z
			1	SPI_CS_2	SPI Channel#2 Chip Select	IO
				MSS_UARTA_TX		IO
			6	MSS_UARTB_TX	Debug: Firmware Trace	O
			7	BSS_UART_TX	Debug: Firmware Trace	O
EA2Ch	QSPI[0]	R11	0	GPIO_8	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	QSPI[0]	QSPI Data IN/OUT	IO
			2	MISO_2	SPI Channel#1 Data Output	IO
EA30h	QSPI[1]	P9	0	GPIO_9	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	QSPI[1]	QSPI Data IN/OUT	IO
			2	MOSI_2	SPI Channel#2 Data Input	IO
EA34h	QSPI[2]	R12	0	GPIO_10	General Purpose IO	IO	Hi-Z	Weak Pull Down
EA34h	QSPI[2]	R12	1	QSPI[2]	QSPI Data IN/OUT	IO
EA38h	QSPI[3]	P10	0	GPIO_11	General Purpose IO	IO	Hi-Z	Weak Pull Down
EA38h	QSPI[3]	P10	1	QSPI[3]	QSPI Data IN/OUT	I
EA3Ch	QSPI_CLK	R10	0	GPIO_7	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	QSPI_CLK	QSPI Clock output from the device. Device operates as a master with the serial flash being a slave	O
			2	SPI_CLK_2	SPI Channel#2 Clock	IO
EA40h	QSPI_CS	P8	0	GPIO_6	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	QSPI_CS	QSPI Chip Select output from the device. Device operates as a master with the serial flash being a slave	O
			2	SPI_CS_2	SPI Channel#2 Chip Select	IO
	NERROR_IN	P7		NERROR_IN	Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware	I	Hi-Z
	WARM_RESET	N12		WARM_RESET	Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.	IO	Hi-Z Input	Open Drain
	NERROR_OUT	N8		NERROR_OUT	Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.	O	Hi-Z	Open Drain
EA50h	TCK	M13	0	GPIO_17	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	TCK	JTAG Clock	I
			2	MSS_UARTB_TX	Debug: Firmware Trace	O
			6	BSS_UART_RX	Debug: Firmware Trace	I
EA54h	TMS	L13	0	GPIO_18	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	TMS	JTAG Test Mode Select	IO
			2	BSS_UART_TX	Debug: Firmware Trace	O
EA58h	TDI	H13	0	GPIO_23	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	TDI	JTAG Test Data In	I
				MSS_UARTA_RX		IO
EA5Ch	TDO	J13	0	GPIO_24	General Purpose IO	IO	Hi-Z
			1	TDO	JTAG Test Data Out	O
				MSS_UARTA_TX		IO
			6	MSS_UARTB_TX	Debug: Firmware Trace	O
			7	BSS_UART_TX	Debug: Firmware Trace	O
			7	SOP0	Sense On Power [Reset] Line Impacts boot mode	I
EA60h	MCU_CLKOUT	N9	0	GPIO_25	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	MCU_CLKOUT	Programmable clock given out to external MCU or the processor	O
			10	BSS_UART_RX	Debug: Firmware Trace	I
EA64h	GPIO_2	N13	0	GPIO_26	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	GPIO_2	General Purpose IO	IO
			7	MSS_UARTB_TX	Debug: Firmware Trace	O
			8	BSS_UART_TX	Debug: Firmware Trace	O
			9	SYNC_OUT	Low frequency Synchronization signal output	O
			10	PMIC_CLKOUT	Dithered clock input to PMIC	O
EA68h	PMIC_CLKOUT	P13	0	GPIO_27	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	PMIC_CLKOUT	Dithered Clock Output for PMIC	O
				SOP2	Sense On Power [Reset] Line Impacts boot mode	I
EA6Ch	SYNC_IN	N10	0	GPIO_28	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	SYNC_IN	Low frequency Synchronization signal input	I
			6	MSS_UARTB_RX	Debug: Firmware Trace	I
EA70h	SYNC_OUT	P11	0	GPIO_29	General Purpose IO	IO	Hi-Z	Weak Pull Down
			1	SYNC_OUT	Low frequency Synchronization signal output	O
				RCOSC_CLK		O
				SOP1	Sense On Power [Reset] Line Impacts boot mode	I
EA74h	RS232_RX	N5	0	GPIO_15	General Purpose IO	IO	Hi-Z	Weak Pull Up
			1	RS232_RX	Debug: Firmware load to RAM	IO
			2	MSS_UARTA_RX	FLASH Programming Bootloader Controlled	I
			6	BSS_UART_TX	Debug: Firmware Trace	O
			7	MSS_UARTB_RX	Debug: Firmware Trace	I
EA78h	RS232_TX	N6	0	GPIO_14	General Purpose IO	IO
			1	RS232_TX	Debug: Firmware load to RAM	IO
			5	MSS_UARTA_TX	FLASH Programming Bootloader Controlled	O
			6	MSS_UARTB_TX	Debug: Firmware Trace	O
			7	BSS_UART_TX	Debug: Firmware Trace	O

(1) Register addresses are of the form FFFF XXXXh, where XXXX is listed here.