ZHCSHS2C may 2017 – january 2022 AWR1443
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 功能方框图
- 5 Revision History
- 6 Device Comparison
- 7 Terminal Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Power-On Hours (POH)
- 8.4 Recommended Operating Conditions
- 8.5 Power Supply Specifications
- 8.6 Power Consumption Summary
- 8.7 RF Specification
- 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
- 8.9
Timing and Switching Characteristics
- 8.9.1 Power Supply Sequencing and Reset Timing
- 8.9.2 Synchronized Frame Triggering
- 8.9.3 Input Clocks and Oscillators
- 8.9.4
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
- 8.9.4.1 Peripheral Description
- 8.9.4.2
MibSPI Transmit and Receive RAM Organization
- 8.9.4.2.1 SPI Timing Conditions
- 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
- 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
- 8.9.4.3 SPI Peripheral Mode I/O Timings
- 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
- 8.9.5 LVDS Interface Configuration
- 8.9.6 General-Purpose Input/Output
- 8.9.7 Controller Area Network Interface (DCAN)
- 8.9.8 Serial Communication Interface (SCI)
- 8.9.9 Inter-Integrated Circuit Interface (I2C)
- 8.9.10 Quad Serial Peripheral Interface (QSPI)
- 8.9.11 JTAG Interface
- 9 Detailed Description
- 10Applications, Implementation, and Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
8.7 RF Specification
over recommended operating conditions
(unless
otherwise noted)
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| Receiver | Noise figure | 76 to 77 GHz | 14 | dB | ||
| 77 to 81 GHz | 15 | |||||
| 1-dB compression point (Out Of Band)(1) | –8 | dBm | ||||
| Maximum gain | 48 | dB | ||||
| Gain range | 24 | dB | ||||
| Gain step size | 2 | dB | ||||
| Image Rejection Ratio (IMRR) | 30 | dB | ||||
| IF bandwidth(2) | 5 | MHz | ||||
| ADC sampling rate (real/complex 2x) | 12.5 | Msps | ||||
| ADC sampling rate (complex 1x) | 6.25 | Msps | ||||
| ADC resolution | 12 | Bits | ||||
| Return loss (S11) | <–10 | dB | ||||
| Gain mismatch variation (over temperature) | ±0.5 | dB | ||||
| Phase mismatch variation (over temperature) | ±3 | ° | ||||
| In-band IIP2 | RX gain =
30dB IF = 1.5, 2 MHz at –12 dBFS |
16 | dBm | |||
| Out-of-band IIP2 | RX gain =
24dB IF = 10 kHz at -10dBm, 1.9 MHz at -30 dBm |
24 | dBm | |||
| Idle Channel Spurs | –90 | dBFS | ||||
| Transmitter | Output power | 12 | dBm | |||
| Amplitude noise | –145 | dBc/Hz | ||||
| Clock subsystem | Frequency range | 76 | 81 | GHz | ||
| Ramp rate | 100 | MHz/µs | ||||
| Phase noise at 1-MHz offset | 76 to 77 GHz | –95 | dBc/Hz | |||
| 77 to 81 GHz | –93 | |||||
(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous
wave Tone (10 kHz) well below the lowest HPF cut-off frequency.
(2) The analog IF stages include high-pass filtering, with two independently
configurable first-order high-pass corner frequencies. The set of available HPF corners is
summarized as follows:
The filtering performed by the digital baseband chain is targeted to provide:
| Available HPF Corner Frequencies (kHz) | |
| HPF1 | HPF2 |
| 175, 235, 350, 700 | 350, 700, 1400, 2800 |
- Less than ±0.5 dB pass-band ripple/droop, and
- Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
Figure 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.
Figure 8-1 Noise Figure, In-band P1dB vs Receiver
Gain