ZHCSHS2C may 2017 – january 2022 AWR1443
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 功能方框图
- 5 Revision History
- 6 Device Comparison
- 7 Terminal Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Power-On Hours (POH)
- 8.4 Recommended Operating Conditions
- 8.5 Power Supply Specifications
- 8.6 Power Consumption Summary
- 8.7 RF Specification
- 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
- 8.9
Timing and Switching Characteristics
- 8.9.1 Power Supply Sequencing and Reset Timing
- 8.9.2 Synchronized Frame Triggering
- 8.9.3 Input Clocks and Oscillators
- 8.9.4
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
- 8.9.4.1 Peripheral Description
- 8.9.4.2
MibSPI Transmit and Receive RAM Organization
- 8.9.4.2.1 SPI Timing Conditions
- 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
- 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
- 8.9.4.3 SPI Peripheral Mode I/O Timings
- 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
- 8.9.5 LVDS Interface Configuration
- 8.9.6 General-Purpose Input/Output
- 8.9.7 Controller Area Network Interface (DCAN)
- 8.9.8 Serial Communication Interface (SCI)
- 8.9.9 Inter-Integrated Circuit Interface (I2C)
- 8.9.10 Quad Serial Peripheral Interface (QSPI)
- 8.9.11 JTAG Interface
- 9 Detailed Description
- 10Applications, Implementation, and Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)
| NO. | PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| 1 | tc(SPC)M | Cycle time, SPICLK(4) | 25 | 256tc(VCLK) | ns | ||
| 2(4) | tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – 4 | 0.5tc(SPC)M + 4 | ns | ||
| tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – 4 | 0.5tc(SPC)M + 4 | ||||
| 3(4) | tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – 4 | 0.5tc(SPC)M + 4 | ns | ||
| tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – 4 | 0.5tc(SPC)M + 4 | ||||
| 4(4) | td(SPCH-SIMO)M | Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0) | 0.5tc(SPC)M – 3 | ns | |||
| td(SPCL-SIMO)M | Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1) | 0.5tc(SPC)M – 3 | |||||
| 5(4) | tv(SPCL-SIMO)M | Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0) | 0.5tc(SPC)M – 10.5 | ns | |||
| tv(SPCH-SIMO)M | Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1) | 0.5tc(SPC)M – 10.5 | |||||
| 6(5) | tC2TDELAY | Setup time CS active until SPICLK high (clock polarity = 0) | CSHOLD = 0 | 0.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 7 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5 | ns | |
| CSHOLD = 1 | 0.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 7 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5 | |||||
| Setup time CS active until SPICLK low (clock polarity = 1) | CSHOLD = 0 | 0.5*tc(SPC)M + (C2TDELAY+2)*tc(VCLK) – 7 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5 | ||||
| CSHOLD = 1 | 0.5*tc(SPC)M + (C2TDELAY+3)*tc(VCLK) – 7 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) + 7.5 | |||||
| 7(5) | tT2CDELAY | Hold time, SPICLK low until CS inactive (clock polarity = 0) | (T2CDELAY + 1) *tc(VCLK) – 7.5 | (T2CDELAY + 1) *tc(VCLK) + 7 | ns | ||
| Hold time, SPICLK high until CS inactive (clock polarity = 1) | (T2CDELAY + 1) *tc(VCLK) – 7.5 | (T2CDELAY + 1) *tc(VCLK) + 7 | |||||
| 8(4) | tsu(SOMI-SPCL)M | Setup time, SPISOMI before SPICLK low (clock polarity = 0) | 5 | ns | |||
| tsu(SOMI-SPCH)M | Setup time, SPISOMI before SPICLK high (clock polarity = 1) | 5 | |||||
| 9(4) | th(SPCL-SOMI)M | Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) | 3 | ns | |||
| th(SPCH-SOMI)M | Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) | 3 | |||||
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Figure 8-7 SPI Controller Mode External Timing (CLOCK PHASE = 1)
Figure 8-8 SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1)