The AWR2243 supports seven differential LVDS IOs/Lanes to support debug where raw ADC data could be extracted. The lane configuration supported is four Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data rates:

• 900 Mbps (450 MHz DDR Clock)
• 600 Mbps (300 MHz DDR Clock)
• 450 Mbps (225 MHz DDR Clock)
• 400 Mbps (200 MHz DDR Clock)
• 300 Mbps (150 MHz DDR Clock)
• 225 Mbps (112.5 MHz DDR Clock)
• 150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

Figure 7-8 LVDS Interface Lane Configuration And Relative Timings