ZHCSL77D April 2020 – January 2022 AWR6443 , AWR6843
PRODUCTION DATA
SIGNAL NAME | PIN TYPE | DESCRIPTION | BALL NO. |
---|---|---|---|
BSS_UART_TX | O | Debug UART Transmit [Radar Block] | F14, H14, K13, N10, N13, N4, N5, R8 |
CAN1_FD_RX | I | CAN1 FD (MCAN) Receive Signal | D13, F14, N10, N4, P12 |
CAN1_FD_TX | O | CAN1 FD (MCAN) Transmit Signal | E14, H14, N5, P10, R14 |
CAN2_FD_RX | I | CAN2 FD (MCAN) Receive Signal | E13 |
CAN2_FD_TX | IO | CAN2 FD (MCAN) Transmit Signal | E15 |
DMM0 | I | Debug Interface (Hardware In Loop) - Data Line | R4 |
DMM1 | I | Debug Interface (Hardware In Loop) - Data Line | P5 |
DMM2 | I | Debug Interface (Hardware In Loop) - Data Line | R5 |
DMM3 | I | Debug Interface (Hardware In Loop) - Data Line | P6 |
DMM4 | I | Debug Interface (Hardware In Loop) - Data Line | R7 |
DMM5 | I | Debug Interface (Hardware In Loop) - Data Line | P7 |
DMM6 | I | Debug Interface (Hardware In Loop) - Data Line | R8 |
DMM7 | I | Debug Interface (Hardware In Loop) - Data Line | P8 |
DMM_CLK | I | Debug Interface (Hardware In Loop) - Clock | N15 |
DMM_MUX_IN | I | Debug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances) | G13, J13, P4 |
DMM_SYNC | I | Debug Interface (Hardware In Loop) - Sync | N14 |
DSS_UART_TX | O | Debug UART Transmit [DSP] | D13, E13, G14, P8, R12 |
EPWM1A | O | PWM Module 1 - Output A | N5, N8 |
EPWM1B | O | PWM Module 1 - Output B | H13, N5, P9 |
EPWM1SYNCI | I | J13 | |
EPWM2A | O | PWM Module 2- Output A | H13, N4, N5, P9 |
EPWM2B | O | PWM Module 2 - Output B | N4 |
EPWM2SYNCO | O | R7 | |
EPWM3A | O | PWM Module 3 - Output A | N4 |
EPWM3SYNCO | O | P6 | |
GPIO_0 | IO | General-purpose I/O | H13 |
GPIO_1 | IO | General-purpose I/O | J13 |
GPIO_2 | IO | General-purpose I/O | K13 |
GPIO_3 | IO | General-purpose I/O | E13 |
GPIO_4 | IO | General-purpose I/O | H14 |
GPIO_5 | IO | General-purpose I/O | F14 |
GPIO_6 | IO | General-purpose I/O | P11 |
GPIO_7 | IO | General-purpose I/O | R12 |
GPIO_8 | IO | General-purpose I/O | R13 |
GPIO_9 | IO | General-purpose I/O | N12 |
GPIO_10 | IO | General-purpose I/O | R14 |
GPIO_11 | IO | General-purpose I/O | P12 |
GPIO_12 | IO | General-purpose I/O | P13 |
GPIO_13 | IO | General-purpose I/O | H13 |
GPIO_14 | IO | General-purpose I/O | N5 |
GPIO_15 | IO | General-purpose I/O | N4 |
GPIO_16 | IO | General-purpose I/O | J13 |
GPIO_17 | IO | General-purpose I/O | P10 |
GPIO_18 | IO | General-purpose I/O | N10 |
GPIO_19 | IO | General-purpose I/O | D13 |
GPIO_20 | IO | General-purpose I/O | E14 |
GPIO_21 | IO | General-purpose I/O | F13 |
GPIO_22 | IO | General-purpose I/O | G14 |
GPIO_23 | IO | General-purpose I/O | R11 |
GPIO_24 | IO | General-purpose I/O | N13 |
GPIO_25 | IO | General-purpose I/O | N8 |
GPIO_26 | IO | General-purpose I/O | K13 |
GPIO_27 | IO | General-purpose I/O | P9 |
GPIO_28 | IO | General-purpose I/O | P4 |
GPIO_29 | IO | General-purpose I/O | G13 |
GPIO_30 | IO | General-purpose I/O | C13 |
GPIO_31 | IO | General-purpose I/O | R4 |
GPIO_32 | IO | General-purpose I/O | P5 |
GPIO_33 | IO | General-purpose I/O | R5 |
GPIO_34 | IO | General-purpose I/O | P6 |
GPIO_35 | IO | General-purpose I/O | R7 |
GPIO_36 | IO | General-purpose I/O | P7 |
GPIO_37 | IO | General-purpose I/O | R8 |
GPIO_38 | IO | General-purpose I/O | P8 |
GPIO_47 | IO | General-purpose I/O | N15 |
I2C_SCL | IO | I2C Clock | G14, N4 |
I2C_SDA | IO | I2C Data | F13, N5 |
LVDS_TXP[0] | O | Differential data Out – Lane 0 | J14 |
LVDS_TXM[0] | O | J15 | |
LVDS_TXP[1] | O | Differential data Out – Lane 1 | K14 |
LVDS_TXM[1] | O | K15 | |
LVDS_CLKP | O | Differential clock Out | L14 |
LVDS_CLKM | O | L15 | |
LVDS_FRCLKP | O | Differential Frame Clock | M14 |
LVDS_FRCLKM | O | M15 | |
MCU_CLKOUT | O | Programmable clock given out to external MCU or the processor | N8 |
MSS_UARTA_RX | I | Main Subsystem - UART A Receive | F14, N4, R11 |
MSS_UARTA_TX | O | Main Subsystem - UART A Transmit | H14, N13, N5, R4 |
MSS_UARTB_RX | IO | Main Subsystem - UART B Receive | N4, P4 |
MSS_UARTB_TX | O | Main Subsystem - UART B Transmit | F14, H14, K13, N13, N5, P10, P7 |
NDMM_EN | I | Debug Interface (Hardware In Loop) Enable - Active Low Signal | N13, N5 |
NERROR_IN | I | Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware | N7 |
NERROR_OUT | O | Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. | N6 |
PMIC_CLKOUT | O | Output Clock from AWR6843 device for PMIC | H13, K13, P9 |
QSPI[0] | IO | QSPI Data Line #0 (Used with Serial Data Flash) | R13 |
QSPI[1] | I | QSPI Data Line #1 (Used with Serial Data Flash) | N12 |
QSPI[2] | I | QSPI Data Line #2 (Used with Serial Data Flash) | R14 |
QSPI[3] | I | QSPI Data Line #3 (Used with Serial Data Flash) | P12 |
QSPI_CLK | O | QSPI Clock (Used with Serial Data Flash) | R12 |
QSPI_CLK_EXT | I | QSPI Clock (Used with Serial Data Flash) | H14 |
QSPI_CS_N | O | QSPI Chip Select (Used with Serial Data Flash) | P11 |
RS232_RX | I | Debug UART (Operates as Bus Master) - Receive Signal | N4 |
RS232_TX | O | Debug UART (Operates as Bus Master) - Transmit Signal | N5 |
SOP[0] | I | Sense On Power - Line#0 | N13 |
SOP[1] | I | Sense On Power - Line#1 | G13 |
SOP[2] | I | Sense On Power - Line#2 | P9 |
SPIA_CLK | IO | SPI Channel A - Clock | E13 |
SPIA_CS_N | IO | SPI Channel A - Chip Select | E15 |
SPIA_MISO | IO | SPI Channel A - Master In Slave Out | E14 |
SPIA_MOSI | IO | SPI Channel A - Master Out Slave In | D13 |
SPIB_CLK | IO | SPI Channel B - Clock | F14, R12 |
SPIB_CS_N | IO | SPI Channel B Chip Select (Instance ID 0) | H14, P11 |
SPIB_CS_N_1 | IO | SPI Channel B Chip Select (Instance ID 1) | G13, J13, P13 |
SPIB_CS_N_2 | IO | SPI Channel B Chip Select (Instance ID 2) | G13, J13, N12 |
SPIB_MISO | IO | SPI Channel B - Master In Slave Out | G14, R13 |
SPIB_MOSI | IO | SPI Channel B - Master Out Slave In | F13, N12 |
SPI_HOST_INTR | O | Out of Band Interrupt to an external host communicating over SPI | P13 |
SYNC_IN | I | Low frequency Synchronization signal input | P4 |
SYNC_OUT | O | Low Frequency Synchronization Signal output | G13, J13, K13, P4 |
TCK | I | JTAG Test Clock | P10 |
TDI | I | JTAG Test Data Input | R11 |
TDO | O | JTAG Test Data Output | N13 |
TMS | I | JTAG Test Mode Signal | N10 |
TRACE_CLK | O | Debug Trace Output - Clock | N15 |
TRACE_CTL | O | Debug Trace Output - Control | N14 |
TRACE_DATA_0 | O | Debug Trace Output - Data Line | R4 |
TRACE_DATA_1 | O | Debug Trace Output - Data Line | P5 |
TRACE_DATA_2 | O | Debug Trace Output - Data Line | R5 |
TRACE_DATA_3 | O | Debug Trace Output - Data Line | P6 |
TRACE_DATA_4 | O | Debug Trace Output - Data Line | R7 |
TRACE_DATA_5 | O | Debug Trace Output - Data Line | P7 |
TRACE_DATA_6 | O | Debug Trace Output - Data Line | R8 |
TRACE_DATA_7 | O | Debug Trace Output - Data Line | P8 |
FRAME_START | O | Pulse signal indicating the start of each frame | N8, K13, P9 |
CHIRP_START | O | Pulse signal indicating the start of each chirp | N8, K13, P9 |
CHIRP_END | O | Pulse signal indicating the end of each chirp | N8, K13, P9 |
WARM_RESET | IO | Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. | N9 |