ZHCS384H November 2011 – July 2022 BQ24160 , BQ24160A , BQ24161 , BQ24161B , BQ24163 , BQ24168
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| INPUT CURRENTS | |||||||
| ISUPPLY | Supply current for control (VIN or VUSB) | VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP | PWM switching | 15 | mA | ||
| PWM NOT switching | 5 | ||||||
| 0°C < TJ < 85°C, High-Z Mode | 175 | μA | |||||
| IBATLEAK | Leakage current from BAT to the Supply | 0°C < TJ < 85°C, VBAT = 4.2V, VUSB = VIN = 0V | 5 | μA | |||
| IBAT_HIZ | Battery discharge current in High Impedance mode, (BAT, SW, SYS) | 0°C< TJ < 85°C, VBAT = 4.2V, VSUPPLY = 5V or 0V, SCL, SDA = 0 V or 1.8V, High-Z Mode | 55 | μA | |||
| POWER-PATH MANAGEMENT | |||||||
| VSYS(REG) | System regulation voltage | Charge Enabled, VBAT < VMINSYS | BQ24160, 1, 1B, 8 | 3.60 | 3.7 | 3.82 | V |
| BQ24163 | 3.3 | 3.4 | 3.5 | ||||
| Battery FET turned off (Charge Disabled, TS Fault or Charging Terminated) | VBATREG + 1.5% | VBATREG + 3.0% | VBATREG + 4.17% | ||||
| VMINSYS | Minimum system regulation voltage | Charge enabled, VBAT < VMINSYS, Input current limit or VINDPM active | BQ24160, 1, 1B, 8 | 3.4 | 3.5 | 3.62 | V |
| BQ24163 | 3.1 | 3.2 | 3.3 | V | |||
| VBSUP1 | Enter supplement mode threshold | VBAT > 2.5V | VBAT –30mV | V | |||
| VBSUP2 | Exit supplement mode threshold | VBAT > 2.5V | VBAT –10mV | V | |||
| ILIM(discharge) | Current limit, discharge or supplement mode | Current monitored in internal FET only. | 7 | A | |||
| tDGL(SC1) | Deglitch time, SYS short circuit during discharge or supplement mode | Measured from (VBAT – VSYS) = 300mV to BAT high-impedance | 250 | μs | |||
| tREC(SC1) | Recovery time, SYS short circuit during discharge or supplement mode | 60 | ms | ||||
| Battery range for BGATE and supplement mode operation | 2.5 | 4.5 | V | ||||
| BATTERY CHARGER | |||||||
| RON(BAT-SYS) | Internal battery charger MOSFET on-resistance | Measured from BAT to SYS, VBAT = 4.2V | YFF pkg | 37 | 57 | mΩ | |
| RGE pkg | 50 | 70 | |||||
| VBATREG | Charge Voltage | Operating in voltage regulation, Programmable range | 3.5 | 4.44 | V | ||
| Voltage regulation accuracy | –1% | 1% | |||||
| ICHARGE | Fast charge current range | VBATSHRT ≤ VBAT < VBAT(REG) programmable range | 550 | 2500 | mA | ||
| Fast charge current accuracy | 0°C to 125°C | –10% | +10% | ||||
| VBATSHRT | Battery short circuit threshold | 100mV Hysteresis | BQ24161, 3, 8 | 1.9 | 2.0 | 2.1 | V |
| BQ24160, 1B | 2.9 | 3.0 | 3.1 | ||||
| IBATSHRT | Battery short circuit current | VBAT < VBATSHRT | 50 | mA | |||
| tDGL(BATSHRT) | Deglitch time for battery short circuit to fastcharge transition | 32 | ms | ||||
| ITERM | Termination charge current accuracy | ITERM = 50mA | –40% | +40% | |||
| ITERM = 100mA | –20% | +20% | |||||
| ITERM ≥ 150mA | –15% | +15% | |||||
| tDGL(TERM) | Deglitch time for charge termination | Both rising and falling, 2mV overdrive, tRISE, tFALL = 100ns | 32 | ms | |||
| VRCH | Recharge threshold voltage | Below VBATREG | 120 | mV | |||
| tDGL(RCH) | Deglitch time | VBAT falling below VRCH, tFALL=100ns | 32 | ms | |||
| VDETECT | Battery detection threshold | During battery detection source cycle | 3.3 | V | |||
| During battery detection sink cycle | 3.0 | ||||||
| IDETECT | Battery detection current before charge done (sink current) | Termination enabled (EN_TERM = 1) | 2.5 | mA | |||
| tDETECT | Battery detection time | Termination enabled (EN_TERM = 1) | 250 | ms | |||
| VIH | PSEL, CD Input high logic level | 1.3 | V | ||||
| VIL | PSEL, CD Input low logic level | 0.4 | V | ||||
| INPUT CURRENT LIMITING | |||||||
| IIN_USB | Input current limit threshold (USB input) | USB charge mode, VUSB = 5V, DC Current pulled from SW | IUSBLIM = USB100 | 90 | 95 | 100 | mA |
| IUSBLIM = USB500 | 450 | 475 | 500 | ||||
| IUSBLIM = USB150 | 135 | 142.5 | 150 | ||||
| IUSBLIM = USB900 | 800 | 850 | 900 | ||||
| IUSBLIM = USB800 | 700 | 750 | 800 | ||||
| IUSBLIM = 1.5A | 1250 | 1400 | 1500 | ||||
| IIN_IN | Input current limit threshold (IN input) | IN charge mode, VIN = 5V, DC Current pulled from SW | IINLIM = 1.5A | 1.35 | 1.5 | 1.65 | A |
| IINLIM = 2.5A | 2.3 | 2.5 | 2.8 | ||||
| VIN_DPM | Input based DPM threshold range | Charge mode, programmable via I2C, both inputs | 4.2 | 4.76 | V | ||
| VIN_DPM threshold accuracy | –2 | +2% | |||||
| VDRV BIAS REGULATOR | |||||||
| VDRV | Internal bias regulator voltage | VSUPPLY > 5.45V | 5 | 5.2 | 5.45 | V | |
| IDRV | DRV output current | 10 | mA | ||||
| VDO_DRV | DRV Dropout voltage (VSUPPLY – VDRV) | ISUPPLY = 1A, VSUPPLY = 5V, IDRV = 10mA | 450 | mV | |||
| STATUS OUTPUT ( STAT, INT) | |||||||
| VOL | Low-level output saturation voltage | IO = 10mA, sink current | 0.4 | V | |||
| IIH | High-level leakage current | VSTAT = VINT = 5V | 1 | µA | |||
| PROTECTION | |||||||
| VUVLO | IC active threshold voltage | VIN rising | 3.6 | 3.8 | 4 | V | |
| VUVLO_HYS | IC active hysteresis | VIN falling from above VUVLO | 120 | 150 | mV | ||
| VSLP | Sleep-mode entry threshold, VSUPPLY-VBAT | 2.0V ≤VBAT ≤VBATREG, VIN falling | 0 | 40 | 100 | mV | |
| VSLP_EXIT | Sleep-mode exit hysteresis | 2.0V ≤VBAT ≤VBATREG | 40 | 100 | 175 | mV | |
| Deglitch time for supply rising above VSLP+VSLP_EXIT | Rising voltage, 2mV over drive, tRISE = 100ns | 30 | ms | ||||
| VBAD_SOURCE | Bad source detection threshold | After Bad Source Detection completes | VIN_DPM – 80 mV | V | |||
| During Bad Source Detection | VIN_DPM + 80 mV | V | |||||
| tDGL(BSD) | Deglitch on bad source detection | 32 | ms | ||||
| VOVP | Input supply OVP threshold voltage | USB, VUSB Rising | 6.3 | 6.5 | 6.7 | V | |
| IN, VIN Rising (BQ24160/1/1B/3) | 10.3 | 10.5 | 10.7 | ||||
| IN, VIN Rising (BQ24168) | 6.3 | 6.5 | 6.7 | ||||
| VOVP(HYS) | VOVP hysteresis | Supply falling from VOVP | 100 | mV | |||
| VBOVP | Battery OVP threshold voltage | VBAT threshold over VOREG to turn off charger during charge | 1.025 × VBATREG | 1.05 × VBATREG | 1.075 × VBATREG | V | |
| VBOVP hysteresis | Lower limit for VBAT falling from above VBOVP | 1 | % of VBATREG | ||||
| tDGL(BOVP) | Battery OVP deglitch | BOVP fault shown in register once tDGL(BOVP) expires. Buck converter shut down immediately when VBAT > VBATOVP | 1 | ms | |||
| VBATUVLO | Battery undervoltage lockout threshold | VBAT rising, 100mV hysteresis | 2.5 | V | |||
| ILIMIT | Cycle-by-cycle current limit | VSYS shorted | 4.1 | 4.9 | 5.6 | A | |
| TSHTDWN | Thermal trip | 165 | °C | ||||
| Thermal hysteresis | 10 | ||||||
| TREG | Thermal regulation threshold | Charge current begins to cut off | 120 | °C | |||
| Safety timer accuracy | (BQ24160/1/1B/3 Only) | –20% | 20% | ||||
| PWM | |||||||
| Internal top reverse blocking MOSFET on-resistance | IIN_LIMIT = 500mA, Measured from USB to PMIDU | 95 | 175 | mΩ | |||
| IIN_LIMIT = 500mA, Measured from IN to PMIDI | 45 | 80 | |||||
| Internal top N-channel Switching MOSFET on-resistance | Measured from PMIDU to SW | 100 | 175 | mΩ | |||
| Measured from PMIDI to SW | 65 | 110 | |||||
| Internal bottom N-channel MOSFET on-resistance | Measured from SW to PGND | 65 | 115 | mΩ | |||
| fOSC | Oscillator frequency | 1.35 | 1.50 | 1.65 | MHz | ||
| DMAX | Maximum duty cycle | 95% | |||||
| DMIN | Minimum duty cycle | 0% | |||||
| BATTERY-PACK NTC MONITOR | |||||||
| VHOT | High temperature threshold | VTS falling | 29.7 | 30 | 30.5 | %VDRV | |
| VHYS(HOT) | Hysteresis on high threshold | VTS rising | 1 | ||||
| VWARM | High temperature threshold | VTS falling | 37.9 | 38.3 | 39.6 | %VDRV | |
| VHYS(WARM) | Hysteresis on high threshold | VTS rising | 1 | ||||
| VCOOL | Low temperature threshold | VTS falling | 56 | 56.5 | 56.9 | %VDRV | |
| VHYS(COOL) | Hysteresis on low threshold | VTS rising | 1 | ||||
| VCOLD | Low temperature threshold | VTS falling | 59.5 | 60 | 60.4 | %VDRV | |
| VHYS(COLD) | Hysteresis on low threshold | VTS rising | 1 | ||||
| TSOFF | TS Disable threshold | VTS rising, 2%VDRV hysteresis | 70 | 73 | %VDRV | ||
| tDGL(TS) | Deglitch time on TS change | 50 | ms | ||||
| D+/D– DETECTION (bq24160) | |||||||
| VD+_SRC | D+ Voltage Source | 0.5 | 0.6 | 0.7 | V | ||
| ID+_SRC | D+ Connection Check Current Source | 7 | 14 | µA | |||
| ID-_SINK | D- Current Sink | 50 | 100 | 150 | µA | ||
| ID_LKG | Leakage Current into D+/D- | D–, switch open | –1 | 1 | µA | ||
| D+, switch open | –1 | 1 | µA | ||||
| VD+_LOW | D+ Low Comparator Threshold | 0.8 | V | ||||
| VD-_LOWdatref | D- Low Comparator Threshold | 250 | 400 | mV | |||
| RD-_DWN | D- Pulldown for Connection Check | 14.25 | 24.8 | kΩ | |||
| BATGD OPERATION | |||||||
| VBATGD | Good Battery threshold | 3.6 | 3.8 | 3.9 | V | ||
| Deglitch for good battery threshold | VBAT rising to HIGH-Z mode, DEFAULT Mode Only | 32 | ms | ||||
| I2C COMPATIBLE INTERFACE | |||||||
| VIH | Input low threshold level | VPULL-UP = 1.8V, SDA and SCL | 1.3 | V | |||
| VIL | Input low threshold level | VPULL-UP = 1.8V, SDA and SCL | 0.4 | V | |||
| VOL | Output low threshold level | IL = 10mA, sink current | 0.4 | V | |||
| IBIAS | High-Level leakage current | VPULL-UP = 1.8V, SDA and SCL | 1 | μA | |||
| tWATCHDOG | Watchdog timer timeout | (BQ24160/1/3 Only) | 30 | s | |||