米6体育平台手机版

ZHCS384H November 2011 – July 2022 BQ24160 , BQ24160A , BQ24161 , BQ24161B , BQ24163 , BQ24168

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

YFF|49
- MXBG102R
RGE|24
- MPQF124G

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND136Y

订购信息

7.5 Electrical Characteristics

Circuit of Figure 9-1, V_SUPPLY = V_USB or V_IN (whichever is supplying the IC), V_UVLO < V_SUPPLY < V_OVP and V_SUPPLY > V_BAT+V_SLP, T_J = -40°C – 125°C and T_J = 25°C for typical values (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
INPUT CURRENTS
I_SUPPLY	Supply current for control (V_IN or V_USB)	V_UVLO < V_SUPPLY < V_OVP and V_SUPPLY > V_BAT+V_SLP	PWM switching		15		mA
		V_UVLO < V_SUPPLY < V_OVP and V_SUPPLY > V_BAT+V_SLP	PWM NOT switching			5
		0°C < T_J < 85°C, High-Z Mode				175	μA
I_BATLEAK	Leakage current from BAT to the Supply	0°C < T_J < 85°C, V_BAT = 4.2V, V_USB = V_IN = 0V				5	μA
I_{BAT_HIZ}	Battery discharge current in High Impedance mode, (BAT, SW, SYS)	0°C< T_J < 85°C, V_BAT = 4.2V, V_SUPPLY = 5V or 0V, SCL, SDA = 0 V or 1.8V, High-Z Mode				55	μA
POWER-PATH MANAGEMENT
V_SYS(REG)	System regulation voltage	Charge Enabled, V_BAT < V_MINSYS	BQ24160, 1, 1B, 8	3.60	3.7	3.82	V
		Charge Enabled, V_BAT < V_MINSYS	BQ24163	3.3	3.4	3.5
		Battery FET turned off (Charge Disabled, TS Fault or Charging Terminated)		V_BATREG + 1.5%	V_BATREG + 3.0%	V_BATREG + 4.17%
V_MINSYS	Minimum system regulation voltage	Charge enabled, V_BAT < V_MINSYS, Input current limit or V_INDPM active	BQ24160, 1, 1B, 8	3.4	3.5	3.62	V
V_MINSYS	Minimum system regulation voltage		BQ24163	3.1	3.2	3.3	V
V_BSUP1	Enter supplement mode threshold	V_BAT > 2.5V			V_BAT –30mV		V
V_BSUP2	Exit supplement mode threshold	V_BAT > 2.5V			V_BAT –10mV		V
I_{LIM(discharge)}	Current limit, discharge or supplement mode	Current monitored in internal FET only.			7		A
t_DGL(SC1)	Deglitch time, SYS short circuit during discharge or supplement mode	Measured from (V_BAT – V_SYS) = 300mV to BAT high-impedance			250		μs
t_REC(SC1)	Recovery time, SYS short circuit during discharge or supplement mode				60		ms
	Battery range for BGATE and supplement mode operation			2.5		4.5	V
BATTERY CHARGER
R_ON(BAT-SYS)	Internal battery charger MOSFET on-resistance	Measured from BAT to SYS, V_BAT = 4.2V	YFF pkg		37	57	mΩ
R_ON(BAT-SYS)	Internal battery charger MOSFET on-resistance	Measured from BAT to SYS, V_BAT = 4.2V	RGE pkg		50	70	mΩ
V_BATREG	Charge Voltage	Operating in voltage regulation, Programmable range		3.5		4.44	V
V_BATREG	Voltage regulation accuracy			–1%		1%
I_CHARGE	Fast charge current range	V_BATSHRT ≤ V_BAT < V_BAT(REG) programmable range		550		2500	mA
I_CHARGE	Fast charge current accuracy	0°C to 125°C		–10%		+10%
V_BATSHRT	Battery short circuit threshold	100mV Hysteresis	BQ24161, 3, 8	1.9	2.0	2.1	V
V_BATSHRT	Battery short circuit threshold	100mV Hysteresis	BQ24160, 1B	2.9	3.0	3.1	V
I_BATSHRT	Battery short circuit current	V_BAT < V_BATSHRT			50		mA
t_DGL(BATSHRT)	Deglitch time for battery short circuit to fastcharge transition				32		ms
I_TERM	Termination charge current accuracy	I_TERM = 50mA		–40%		+40%
		I_TERM = 100mA		–20%		+20%
		I_TERM ≥ 150mA		–15%		+15%
t_DGL(TERM)	Deglitch time for charge termination	Both rising and falling, 2mV overdrive, t_RISE, t_FALL = 100ns			32		ms
V_RCH	Recharge threshold voltage	Below V_BATREG			120		mV
t_DGL(RCH)	Deglitch time	VBAT falling below VRCH, tFALL=100ns			32		ms
V_DETECT	Battery detection threshold	During battery detection source cycle			3.3		V
V_DETECT	Battery detection threshold	During battery detection sink cycle			3.0		V
I_DETECT	Battery detection current before charge done (sink current)	Termination enabled (EN_TERM = 1)			2.5		mA
t_DETECT	Battery detection time	Termination enabled (EN_TERM = 1)			250		ms
V_IH	PSEL, CD Input high logic level			1.3			V
V_IL	PSEL, CD Input low logic level					0.4	V
INPUT CURRENT LIMITING
I_{IN_USB}	Input current limit threshold (USB input)	USB charge mode, V_USB = 5V, DC Current pulled from SW	I_USBLIM = USB100	90	95	100	mA
			I_USBLIM = USB500	450	475	500
			I_USBLIM = USB150	135	142.5	150
			I_USBLIM = USB900	800	850	900
			I_USBLIM = USB800	700	750	800
			I_USBLIM = 1.5A	1250	1400	1500
I_{IN_IN}	Input current limit threshold (IN input)	IN charge mode, V_IN = 5V, DC Current pulled from SW	I_INLIM = 1.5A	1.35	1.5	1.65	A
I_{IN_IN}	Input current limit threshold (IN input)	IN charge mode, V_IN = 5V, DC Current pulled from SW	I_INLIM = 2.5A	2.3	2.5	2.8	A
V_{IN_DPM}	Input based DPM threshold range	Charge mode, programmable via I²C, both inputs		4.2		4.76	V
	V_{IN_DPM} threshold accuracy			–2		+2%
VDRV BIAS REGULATOR
V_DRV	Internal bias regulator voltage	V_SUPPLY > 5.45V		5	5.2	5.45	V
I_DRV	DRV output current			10			mA
V_{DO_DRV}	DRV Dropout voltage (V_SUPPLY – V_DRV)	I_SUPPLY = 1A, V_SUPPLY = 5V, I_DRV = 10mA				450	mV
STATUS OUTPUT ( STAT, INT)
V_OL	Low-level output saturation voltage	I_O = 10mA, sink current				0.4	V
I_IH	High-level leakage current	V_STAT = V_INT = 5V				1	µA
PROTECTION
V_UVLO	IC active threshold voltage	V_IN rising		3.6	3.8	4	V
V_{UVLO_HYS}	IC active hysteresis	V_IN falling from above V_UVLO		120	150		mV
V_SLP	Sleep-mode entry threshold, V_SUPPLY-V_BAT	2.0V ≤V_BAT ≤V_BATREG, V_IN falling		0	40	100	mV
V_{SLP_EXIT}	Sleep-mode exit hysteresis	2.0V ≤V_BAT ≤V_BATREG		40	100	175	mV
	Deglitch time for supply rising above V_SLP+V_{SLP_EXIT}	Rising voltage, 2mV over drive, t_RISE = 100ns			30		ms
V_{BAD_SOURCE}	Bad source detection threshold	After Bad Source Detection completes			V_{IN_DPM} – 80 mV		V
V_{BAD_SOURCE}	Bad source detection threshold	During Bad Source Detection			V_{IN_DPM} + 80 mV		V
t_DGL(BSD)	Deglitch on bad source detection				32		ms
V_OVP	Input supply OVP threshold voltage	USB, V_USB Rising		6.3	6.5	6.7	V
		IN, V_IN Rising (BQ24160/1/1B/3)		10.3	10.5	10.7
		IN, V_IN Rising (BQ24168)		6.3	6.5	6.7
V_OVP(HYS)	V_OVP hysteresis	Supply falling from V_OVP			100		mV
V_BOVP	Battery OVP threshold voltage	V_BAT threshold over V_OREG to turn off charger during charge		1.025 × V_BATREG	1.05 × V_BATREG	1.075 × V_BATREG	V
	V_BOVP hysteresis	Lower limit for V_BAT falling from above V_BOVP			1		% of V_BATREG
t_DGL(BOVP)	Battery OVP deglitch	BOVP fault shown in register once t_DGL(BOVP) expires. Buck converter shut down immediately when V_BAT > V_BATOVP			1		ms
V_BATUVLO	Battery undervoltage lockout threshold	V_BAT rising, 100mV hysteresis			2.5		V
I_LIMIT	Cycle-by-cycle current limit	V_SYS shorted		4.1	4.9	5.6	A
T_SHTDWN	Thermal trip				165		°C
	Thermal hysteresis				10		°C
T_REG	Thermal regulation threshold	Charge current begins to cut off			120		°C
	Safety timer accuracy	(BQ24160/1/1B/3 Only)		–20%		20%
PWM
	Internal top reverse blocking MOSFET on-resistance	I_{IN_LIMIT} = 500mA, Measured from USB to PMIDU			95	175	mΩ
	Internal top reverse blocking MOSFET on-resistance	I_{IN_LIMIT} = 500mA, Measured from IN to PMIDI			45	80	mΩ
	Internal top N-channel Switching MOSFET on-resistance	Measured from PMIDU to SW			100	175	mΩ
	Internal top N-channel Switching MOSFET on-resistance	Measured from PMIDI to SW			65	110	mΩ
	Internal bottom N-channel MOSFET on-resistance	Measured from SW to PGND			65	115	mΩ
f_OSC	Oscillator frequency			1.35	1.50	1.65	MHz
D_MAX	Maximum duty cycle				95%
D_MIN	Minimum duty cycle			0%
BATTERY-PACK NTC MONITOR
V_HOT	High temperature threshold	V_TS falling		29.7	30	30.5	%V_DRV
V_HYS(HOT)	Hysteresis on high threshold	V_TS rising			1		%V_DRV
V_WARM	High temperature threshold	V_TS falling		37.9	38.3	39.6	%V_DRV
V_HYS(WARM)	Hysteresis on high threshold	V_TS rising			1		%V_DRV
V_COOL	Low temperature threshold	V_TS falling		56	56.5	56.9	%V_DRV
V_HYS(COOL)	Hysteresis on low threshold	V_TS rising			1		%V_DRV
V_COLD	Low temperature threshold	V_TS falling		59.5	60	60.4	%V_DRV
V_HYS(COLD)	Hysteresis on low threshold	V_TS rising			1		%V_DRV
TSOFF	TS Disable threshold	V_TS rising, 2%V_DRV hysteresis		70		73	%V_DRV
t_DGL(TS)	Deglitch time on TS change				50		ms
D+/D– DETECTION (bq24160)
V_{D+_SRC}	D+ Voltage Source			0.5	0.6	0.7	V
I_{D+_SRC}	D+ Connection Check Current Source			7		14	µA
I_{D-_SINK}	D- Current Sink			50	100	150	µA
I_{D_LKG}	Leakage Current into D+/D-	D–, switch open		–1		1	µA
I_{D_LKG}	Leakage Current into D+/D-	D+, switch open		–1		1	µA
V_{D+_LOW}	D+ Low Comparator Threshold			0.8			V
V_{D-_LOWdatref}	D- Low Comparator Threshold			250		400	mV
R_{D-_DWN}	D- Pulldown for Connection Check			14.25		24.8	kΩ
BATGD OPERATION
V_BATGD	Good Battery threshold			3.6	3.8	3.9	V
	Deglitch for good battery threshold	V_BAT rising to HIGH-Z mode, DEFAULT Mode Only			32		ms
I²C COMPATIBLE INTERFACE
V_IH	Input low threshold level	V_PULL-UP = 1.8V, SDA and SCL		1.3			V
V_IL	Input low threshold level	V_PULL-UP = 1.8V, SDA and SCL				0.4	V
V_OL	Output low threshold level	I_L = 10mA, sink current				0.4	V
I_BIAS	High-Level leakage current	V_PULL-UP = 1.8V, SDA and SCL			1		μA
t_WATCHDOG	Watchdog timer timeout	(BQ24160/1/3 Only)		30			s