The host initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 8-8. All I²C-compatible devices should recognize a start condition.

Figure 8-8 START and STOP Condition

The host then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the host ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 8-9). All devices recognize the address sent by the host and compare it to their internal fixed addresses. Only the target device with a matching address generates an acknowledge (see Figure 8-10) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the host knows that communication link with a target has been established.

Figure 8-9 Bit Transfer on the Serial Interface

The host generates further SCL cycles to either transmit data to the target (R/W bit 1) or receive data from the target (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the host or by the target, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the host generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 8-11). This releases the bus and stops the communication link with the addressed target. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the host needs sending a STOP condition to prevent the target I²C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section result in FFh being read out.

Figure 8-10 Acknowledge on the I²C Bus

Figure 8-11 Bus Protocol