11.1 Layout Guidelines

The minimum VBUS and BAT capacitors, CVBUS and CBAT, of 1 uF are required to be placed as close as possible between the respective pins and the IC ground pin. Higher bulk capacitance values and additional high frequency (< 0.1 uF) bypass capacitors are allowed. Next, the resistor on ISET, RISET, and on VDPM, RVDPM, should be placed as close as possible to the respective pins and the IC ground pin. The TS pullup resistor, RVTSB or RT1, can then be placed between the VTSB and TS pins. Optional capacitors up to 1.0 uF on TS, CTS, and VTSB, CVTSB, can be placed to minimize noise coupling.

11.2 Layout Example

Figure 16. Recommended Layout