ZHCSBL6D september 2013 – april 2023 BQ24296 , BQ24297
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DPDM_EN | TMR2X_EN | BATFET_Disable | Reserved | Reserved | Reserved | INT_MASK[1] | INT_MASK[0] |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write |
| BIT | FIELD | TYPE | RESET | DESCRIPTION | NOTE |
|---|---|---|---|---|---|
| Force DPDM detection | |||||
| Bit 7 | IINDET_EN | R/W | 0 | 0 – Not in Input current limit detection; 1 – Force Input current limit detection when VBUS power is presence | Default: Not in Input current limit detection (0), Back to 0 after detection complete |
| Safety Timer Setting during Input DPM and Thermal Regulation | |||||
| Bit 6 | TMR2X_EN | R/W | 1 | 0 – Safety timer not slowed by 2X during input DPM or thermal regulation, 1 – Safety timer slowed by 2X during input DPM or thermal regulation | Default: Safety timer slowed by 2X (1) |
| Force BATFET Off | |||||
| Bit 5 | BATFET_Disable | R/W | 0 | 0 – Allow BATFET (Q4) turn on, 1 – Turn off BATFET (Q4) | Default: Allow BATFET (Q4) turn on(0) |
| Bit 4 | Reserved | R/W | 0 | 0 - Reserved | |
| Bit 3 | Reserved | R/W | 1 | 1 - Reserved | |
| Bit 2 | Reserved | R/W | 0 | 0 - Reserved | |
| Bit 1 | INT_MASK[1] | R/W | 1 | 0 – No INT during CHRG_FAULT, 1 – INT on CHRG_FAULT | Default: INT on CHRG_FAULT (1) |
| Bit 0 | INT_MASK[0] | R/W | 1 | 0 – No INT during BAT_FAULT, 1 – INT on BAT_FAULT | Default: INT on BAT_FAULT (1) |