11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize the high-frequency current path loop (see Figure 26) is important to prevent electrical and magnetic field radiation and high-frequency resonance problems. Here is a PCB layout priority list for proper layout. Layout of the PCB according to this specific order is essential.

1. Place the input capacitor as close as possible to switching the MOSFET supply and ground connections and use the shortest possible copper trace connection. These parts should be placed on the same layer of PCB instead of on different layers using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals, keeping the gate-drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize loop area), and do not route the sense leads through a high-current path (see Figure 27 for Kelvin connection for best current accuracy). Place a decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath the IC, use the copper pour for analog ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect the analog ground to GND. Connect the analog ground and power ground together using the power pad as the single ground connection point. Or use a 0-Ω resistor to tie the analog ground to power ground (the thermal pad should tie to analog ground in this case). A star-connection under the tharmal pad is highly recommended.
8. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other layers.
9. Decoupling capacitors should be placed next to the IC pins; make the trace connections as short as possible.
10. All via sizes and numbers should be adequate for a given current path.

See the EVM design (SLUU396) for recommended component placement of trace and via locations.

For VQFN information, see SCBA017 and SLUA271.

11.2 Layout Example

Figure 26. High Frequency Current Path

Figure 27. Sensing Resistor PCB Layout