9.3.23 Manual Reset Timer and Reset Output (MR and RESET)

The MR input has an internal pull-up to BAT, and MR is functional only when BAT is present or when VIN is valid, stable, and charge is enabled. If MR input is asserted during a transient condition while VIN ramps up the IC may incorrectly turn off the SYS buck output, therefore MR should not be asserted during this condition in order to avoid unwanted shutdown of SYS output rail.The input conditions can be adjusted by using MRWAKE bits for the wake conditions and MRRESET bits for the reset conditions. When a wake condition is met, a 128-µs pulse is sent on INT to notify the host, and the WAKE1 and/or WAKE2 bits are updated on I²C. The MR_WAKE bits and RESET FAULT bits are not cleared until the Push-button Control Register is read from I²C.  

When a MR reset condition is met, a 128us pulse is sent on INT to notify the host and a RESET signal is asserted. A reset pulse occurs with duration of t_{RESET_D} only one time after each valid MRRESET condition. The MR pin must be released (go high) and then driven low for the MRWAKE period before RESET asserts again. After RESET is asserted with battery only present, the device enters either Ship mode or Hi-Z mode depending on MRREC register settings. For details on how to properly enter Ship Mode through MR, see Ship Mode Entry and Exit.After RESET is asserted with a valid V_IN present, the device resumes operation prior to the MR button press.  If SYS was disabled prior to RESET, the SYS output is re-enabled if recovering into Hi-Z or Active Battery.

The MRRESET_VIN register can be configured to have RESET asserted by a button press only, or by a button press and V_IN present (V_UVLO + V_SLP< V_IN< V_OVP).