The device integrates a low quiscent current switching regulator with DCS control allowing high efficiency down to 10-µA load currents. DCS control combines the advantages of hysteretic and voltage mode control. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. During PWM mode, it operates in continuous conduction mode, with a frequency up to 2 MHz. If the load current decreases, the converter enters a power save mode to maintain high efficiency down to light loads. In this mode, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shut down to achieve a low quiescent current. The duration of the sleep period depends on the load current and the inductor peak current. For optimal operation and maximum power delivery allow V_PMID > V_SYS + 0.7V.

The output voltage is programmable using the SYS_SEL and SYS_VOUT bits in the SYS VOUT control register.

The SW output is enabled using the EN_SYS_OUT bit in the register. This bit is for testing and debug only and not intended to be used in the final system. When the device is enabled, the internal reference is powered up and the device enters softstart, starts switching, and ramps up the output voltage. When SW is disabled, the output is in shutdown mode in a low quiescent state. The device provides automatic output voltage discharge so the output voltage will ramp up from zero once the device in enabled again. Once SYS has been disabled, either V_IN needs to be connected or the MR button must be held low for the t_RESET duration to re-enable SYS.

The output is optimized for operation with a 2.2-µH inductor and 10-µF output capacitor. Table 9-6 shows the recommended LC output filter combinations.

The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point where the part enters and exits Pulse Frequency Modulation to lower the power consumed at low loads, the output voltage ripple and the efficiency. The selected inductor must be selected for its DC resistance and saturation current. The inductor ripple current (ΔI_L) can be estimated according to Equation 7.

Use Equation 8 to calculate the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current. As the size of the inductor decreases, the saturation “knee” must be carefully considered to ensure that the inductance does not decrease during higher load condition or transient. This is recommended because during a heavy load transient the inductor current rises above the calculated value. A more conservative way is to select the inductor saturation current above the high-side MOSFET switch current.

Where

• F = Switching Frequency
• L = Inductor Value
• ΔI_L = Peak to Peak inductor ripple current
• I_L(max) = Maximum Inductor current

In DC/DC converter applications, the efficiency is affected by the inductor AC resistance and by the inductor DCR value.

Table 9-7 shows recommended inductor series from different suppliers.

The PWM allows the use of small ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Because the PWM converter has a pulsating input current, a low ESR input capacitor is required on PMID for the best voltage filtering to ensure proper function of the device and to minimize input voltage spikes. For most applications a 10-µF capacitor value is sufficient. The PMID capacitor can be increased to 22 µF for better input voltage filtering.

Table 9-8 shows the recommended input/output capacitors.