The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 9-7. All I²C-compatible devices should recognize a start condition.

Figure 9-7 Start Stop Condition

The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 9-8). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates and acknowledge (see Figure 9-9) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a slave has been established.

Figure 9-8 Bit Transfer on the Serial Interface

Figure 9-9 Acknowledge on the I²C Bus

The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which on is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 9-10). This releases the bus and stops the communication link with the addressed slave. All I²C compatible devices must recognize the STOP condition. Upon the receipt of a STOP condition, all devices know that the bus is released, and wait for a START condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I²C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section results in 0xFFh being read out.

Figure 9-10 Bus Protocol