ZHCSJZ9B june   2019  – august 2023 BQ25155

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Device Key Default Settings
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Linear Charger and Power Path
        1. 9.3.1.1 Battery Charging Process
          1. 9.3.1.1.1 Pre-Charge
          2. 9.3.1.1.2 Fast Charge
          3. 9.3.1.1.3 Pre-Charge to Fast Charge Transitions and Charge Current Ramping
          4. 9.3.1.1.4 Termination
        2. 9.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 9.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 9.3.1.4 Battery Supplement Mode
      2. 9.3.2  Protection Mechanisms
        1. 9.3.2.1 Input Over-Voltage Protection
        2. 9.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 9.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 9.3.2.4 Battery Short and Over Current Protection
        5. 9.3.2.5 PMID Short Circuit
      3. 9.3.3  ADC
        1. 9.3.3.1 ADC Operation in Active Battery Mode and Low Power Mode
        2. 9.3.3.2 ADC Operation When VIN Present
        3. 9.3.3.3 ADC Measurements
        4. 9.3.3.4 ADC Programmable Comparators
      4. 9.3.4  VDD LDO
      5. 9.3.5  Load Switch/LDO Output and Control
      6. 9.3.6  PMID Power Control
      7. 9.3.7  System Voltage (PMID) Regulation
      8. 9.3.8  MR Wake and Reset Input
        1. 9.3.8.1 MR Wake or Short Button Press Functions
        2. 9.3.8.2 MR Reset or Long Button Press Functions
      9. 9.3.9  14-Second Watchdog for HW Reset
      10. 9.3.10 Faults Conditions and Interrupts ( INT)
        1. 9.3.10.1 Flags and Fault Condition Response
      11. 9.3.11 Power Good ( PG) Pin
      12. 9.3.12 External NTC Monitoring (TS)
        1. 9.3.12.1 TS Thresholds
      13. 9.3.13 External NTC Monitoring (ADCIN)
      14. 9.3.14 I2C Interface
        1. 9.3.14.1 F/S Mode Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 Ship Mode
      2. 9.4.2 Low Power
      3. 9.4.3 Active Battery
      4. 9.4.4 Charger/Adapter Mode
      5. 9.4.5 Power-Up/Down Sequencing
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input (IN/PMID) Capacitors
        2. 10.2.2.2 VDD, LDO Input and Output Capacitors
        3. 10.2.2.3 TS
        4. 10.2.2.4 Recommended Passive Components
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 静电放电警告
    6. 13.6 Trademarks
    7. 13.7 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.3.5 Load Switch/LDO Output and Control

The device integrates a low Iq load switch which can also be used as a regulated output. The LDO/LS has a dedicated input pin VINLS and can support up to 150 mA of load current.

The LS/LDO may be enabled/disabled through I2C. The output voltage is programmable using the LS_LDO bits in the registers. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to VINLS pin.

The output voltage is programmable using the LS_LDO bits in the registers.The LS/LDO voltage is calculated using the following equation: VLSLDO = 0.6 V + LS_LDOCODE × 100 mV up to 3.7 V. All higher codes will set the output to 3.7 V.

Table 9-3 LDO Mode Control
I2C EN_LS_LDOLS_CONFIGLS/LDO OUTPUT
00Pulldown
01Pulldown
10LDO
11Load Switch

The current capability of the LDO will depend on the VINLS input voltage and the programmed output voltage. When the LS/LDO output is disabled through the register, an internal pull-down will discharge the output.

The LDO has output current limit protection, limiting the output current in the event of a short in the output. When the LDO output current limit trips and is active for at least 1 ms, the device will set a flag and send an interrupt to the host. The LDO may be set to operate as a load switch by setting the LS_SWITCH_CONFG bit. Note that in order to change the configuration the LDO must be disabled first, then the LS_SWITCH_CONFG bit is set for it to take effect.This is not the case when updating the LDO output voltage which can be done on the fly without the need of disabling the LDO first.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |