The I²C interface allows the user to easily implement the JEITA standard for systems where the battery pack thermistor is monitored by the host. Additionally, the device provides a flexible voltage based TS input for monitoring the battery pack NTC thermistor. The NTC thermistor is biased by the device with I_{TS_BIAS} and the resulting voltage at TS is monitored to determine that the battery is at a safe temperature during charging. The TS pin is not biased continuously, instead it is biased only when the voltage at the pin is being sampled (for about 25ms in 225ms intervals when VIN is present. Note that the TS biasing cannot be disabled when VIN is present.

The part can be configured to meet JEITA requirements or a simpler HOT/COLD function only. Additionally, the TS charger control function can be disabled. To satisfy the JEITA requirements, four temperature thresholds are monitored: the cold battery threshold, the cool battery threshold, the warm battery threshold, and the hot battery threshold. These temperatures correspond to the V_COLD, V_COOL, V_WARM, and V_HOT thresholds in the Electrical Characteristics table. Charging and safety timers are suspended when V_TS < V_HOT or V_TS > V_COLD. When V_COOL < V_TS < V_COLD, the charging current is reduced to the value programmed in the TS_FASTCHGCTRL register. Note that the current steps for fast charge in the COOL region, just as those in normal fast charge, are multiples of the fast charge LSB value (1.25 mA by default). So in the case where the calculated scaled down current for the COOL region falls in between charge current steps, the device will round down the charge current to the nearest step. For example, if the fast charge current is set for 15 mA (ICHG = 1100) and TS_FASTCHARGE =111 (0.125*ICHG), the charge current in the COOL region will be 1.25 mA instead of the calculated 1.85 mA.

When V_HOT < V_TS < V_WARM, the battery regulation voltage is reduced to the value programmed in the TS_FASTCHGCTRL register.

Regardless of whether the part is configured for JEITA, HOT/COLD, or disabled, when a TS fault occurs, a 128-µs pulse is sent on the INT output, and the FAULT bits of the register are updated over I²C. The FAULT bits are not cleared until they are read over I²C. This allows the host processor to take action if a different behavior than the pre-set function is needed. Alternately, the TS pin voltage can be read by the host if VIN is present or when BAT is present, so the appropriate action can be taken by the host.