米6体育平台手机版

Table 9-8 lists the memory-mapped registers for the I²C registers. All register offset addresses not listed in Table 9-8 should be considered as reserved locations and the register contents should not be modified.

Table 9-8 I²C Registers

Address	Acronym	Register Name	Section
0x0	STAT0	Charger Status 0	Go
0x1	STAT1	Charger Status 1	Go
0x2	STAT2	ADC Status	Go
0x3	FLAG0	Charger Flags 0	Go
0x4	FLAG1	Charger Flags 1	Go
0x5	FLAG2	ADC Flags	Go
0x6	FLAG3	Timer Flags	Go
0x7	MASK0	Interrupt Masks 0	Go
0x8	MASK1	Interrupt Masks 1	Go
0x9	MASK2	Interrupt Masks 2	Go
0xA	MASK3	Interrupt Masks 3	Go
0x12	VBAT_CTRL	Battery Voltage Control	Go
0x13	ICHG_CTRL	Fast Charge Current Control	Go
0x14	PCHRGCTRL	Pre-Charge Current Control	Go
0x15	TERMCTRL	Termination Current Control	Go
0x16	BUVLO	Battery UVLO and Current Limit Control	Go
0x17	CHARGERCTRL0	Charger Control 0	Go
0x18	CHARGERCTRL1	Charger Control 1	Go
0x19	ILIMCTRL	Input Corrent Limit Control	Go
0x1D	LDOCTRL	LDO Control	Go
0x30	MRCTRL	MR Control	Go
0x35	ICCTRL0	IC Control 0	Go
0x36	ICCTRL1	IC Control 1	Go
0x37	ICCTRL2	IC Control 2	Go
0x40	ADCCTRL0	ADC Control 0	Go
0x41	ADCCTRL1	ADC Control 1	Go
0x42	ADC_DATA_VBAT_M	ADC VBAT Measurement MSB	Go
0x43	ADC_DATA_VBAT_L	ADC VBAT Measurement LSB	Go
0x44	ADC_DATA_TS_M	ADC TS Measurement MSB	Go
0x45	ADC_DATA_TS_L	ADC TS Measurement LSB	Go
0x46	ADC_DATA_ICHG_M	ADC ICHG Measurement MSB	Go
0x47	ADC_DATA_ICHG_L	ADC ICHG Measurement LSB	Go
0x48	ADC_DATA_ADCIN_M	ADC ADCIN Measurement MSB	Go
0x49	ADC_DATA_ADCIN_L	ADC ADCIN Measurement LSB	Go
0x4A	ADC_DATA_VIN_M	ADC VIN Measurement MSB	Go
0x4B	ADC_DATA_VIN_L	ADC VIN Measurement LSB	Go
0x4C	ADC_DATA_PMID_M	ADC VPMID Measurement MSB	Go
0x4D	ADC_DATA_PMID_L	ADC VPMID Measurement LSB	Go
0x4E	ADC_DATA_IIN_M	ADC IIN Measurement MSB	Go
0x4F	ADC_DATA_IIN_L	ADC IIN Measurement LSB	Go
0x52	ADCALARM_COMP1_M	ADC Comparator 1 Threshold MSB	Go
0x53	ADCALARM_COMP1_L	ADC Comparator 1 Threshold LSB	Go
0x54	ADCALARM_COMP2_M	ADC Comparator 2 Threshold MSB	Go
0x55	ADCALARM_COMP2_L	ADC Comparator 2 Threshold LSB	Go
0x56	ADCALARM_COMP3_M	ADC Comparator 3 Threshold MSB	Go
0x57	ADCALARM_COMP3_L	ADC Comparator 3 Threshold LSB	Go
0x58	ADC_READ_EN	ADC Channel Enable	Go
0x61	TS_FASTCHGCTRL	TS Charge Control	Go
0x62	TS_COLD	TS Cold Threshold	Go
0x63	TS_COOL	TS Cool Threshold	Go
0x64	TS_WARM	TS Warm Threshold	Go
0x65	TS_HOT	TS Hot Threshold	Go
0x6F	DEVICE_ID	Device ID	Go

Complex bit access types are encoded to fit into small table cells. Table 9-9 shows the codes that are used for access types in this section.

Table 9-9 I²C Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	C R	to Clear Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

9.5.1.1 STAT0 Register (Address = 0x0) [reset = X]

STAT0 is shown in Figure 9-16 and described in Table 9-10.

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Figure 9-16 STAT0 Register

7	6	5	4	3	2	1	0
RESERVED	CHRG_CV_STAT	CHARGE_DONE_STAT	IINLIM_ACTIVE_STAT	VDPPM_ACTIVE_STAT	VINDPM_ACTIVE_STAT	THERMREG_ACTIVE_STAT	VIN_PGOOD_STAT
R-X	R-X	R-X	R-X	R-X	R-X	R-X	R-X

Table 9-10 STAT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	X	Reserved
6	CHRG_CV_STAT	R	X	Constant Voltage Charging Mode (Taper Mode) Status 1b0 = Not Active 1b1 = Active
5	CHARGE_DONE_STAT	R	X	Charge Done Status 1b0 = Not Active 1b1 = Active
4	IINLIM_ACTIVE_STAT	R	X	Input Current Limit Status 1b0 = Not Active 1b1 = Active
3	VDPPM_ACTIVE_STAT	R	X	DPPM Status 1b0 = Not Active 1b1 = Active
2	VINDPM_ACTIVE_STAT	R	X	VINDPM Status 1b0 = Not Active 1b1 = Active
1	THERMREG_ACTIVE_STAT	R	X	Thermal Regulation Status 1b0 = Not Active 1b1 = Active
0	VIN_PGOOD_STAT	R	X	VIN Power Good Status 1b0 = Not Good 1b1 = V_IN > V_UVLO and V_IN > V_BAT + V_SLP and V_IN < V_OVP

9.5.1.2 STAT1 Register (Address = 0x1) [reset = X]

STAT1 is shown in Figure 9-17 and described in Table 9-11.

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Figure 9-17 STAT1 Register

7	6	5	4	3	2	1	0
VIN_OVP_FAULT_STAT	RESERVED	BAT_OCP_FAULT_STAT	BAT_UVLO_FAULT_STAT	TS_COLD_STAT	TS_COOL_STAT	TS_WARM_STAT	TS_HOT_STAT
R-X	R-X	R-X	R-X	R-X	R-X	R-X	R-X

Table 9-11 STAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VIN_OVP_FAULT_STAT	R	X	VIN Overvoltage Status 1b0 = Not Active 1b1 = Active
6	RESERVED	R	X	Reserved
5	BAT_OCP_FAULT_STAT	R	X	Battery Over-Current Protection Status 1b0 = Not Active 1b1 = Active
4	BAT_UVLO_FAULT_STAT	R	X	Battery voltage below BATUVLO Level Status 1b0 = V_BAT > V_BATUVLO 1b1 = V_BAT < V_BATUVLO
3	TS_COLD_STAT	R	X	TS Cold Status - V_TS > V_COLD (charging suspended) 1b0 = Not Active 1b1 = Active
2	TS_COOL_STAT	R	X	TS Cool Status - V_COOL < V_TS < V_COLD (charging current reduced by value set by TS_Registers) 1b0 = Not Active 1b1 = Active
1	TS_WARM_STAT	R	X	TS Warm - V_WARM > V_TS >V_HOT (charging voltage reduced by value set by TS_Registers) 1b0 = Not Active 1b1 = Active
0	TS_HOT_STAT	R	X	TS Hot Status - V_TS < V_HOT (charging suspended) 1b0 = Not Active 1b1 = Active

9.5.1.3 STAT2 Register (Address = 0x2) [reset = X]

STAT2 is shown in Figure 9-18 and described in Table 9-12.

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Figure 9-18 STAT2 Register

7	6	5	4	3	2	1	0
RESERVED	COMP1_ALARM_STAT	COMP2_ALARM_STAT	COMP3_ALARM_STAT	RESERVED			TS_OPEN_STAT
R-X	R-X	R-X	R-X	R-X			R-X

Table 9-12 STAT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	X	Reserved
6	COMP1_ALARM_STAT	R	X	COMP1 Status 1b0 = Selected ADC measurement does not meet condition set by 1_ADCALARM_ABOVE bit 1b1 = Selected ADC measurement meets condition set by 1_ADCALARM_ABOVE bit
5	COMP2_ALARM_STAT	R	X	COMP2 Status 1b0 = Selected ADC measurement does not meet condition set by 2_ADCALARM_ABOVE bit 1b1 = Selected ADC measurement meets condition set by 2_ADCALARM_ABOVE bit
4	COMP3_ALARM_STAT	R	X	COMP3 Status 1b0 = Selected ADC measurement does not meet condition set by 1_ADCALARM_ABOVE bit 1b1 = Selected ADC measurement meets condition set by 2_ADCALARM_ABOVE bit
3-1	RESERVED	R	X	Reserved
0	TS_OPEN_STAT	R	X	TS Open Status 1b0 = V_TS < V_OPEN 1b1 = V_TS > V_OPEN

9.5.1.4 FLAG0 Register (Address = 0x3) [reset = 0x0]

FLAG0 is shown in Figure 9-19 and described in Table 9-13.

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Clear on Read

Figure 9-19 FLAG0 Register

7	6	5	4	3	2	1	0
RESERVED	CHRG_CV_FLAG	CHARGE_DONE_FLAG	IINLIM_ACTIVE_FLAG	VDPPM_ACTIVE_FLAG	VINDPM_ACTIVE_FLAG	THERMREG_ACTIVE_FLAG	VIN_PGOOD_FLAG
RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0

Table 9-13 FLAG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	RC	1b0	Reserved
6	CHRG_CV_FLAG	RC	1b0	Constant Voltage Charging Mode (Taper Mode) Flag 1b0 = CV Mode Entry not detected 1b1 = CV Mode Entry detected
5	CHARGE_DONE_FLAG	RC	1b0	Charge Done Flag 1b0 = Charge Done (Termination) not detected 1b1 = Charge Done (Termination) detected
4	IINLIM_ACTIVE_FLAG	RC	1b0	Input Current Limit Flag 1b0 = Input Current Limit not detected 1b1 = Input Current Limit detected
3	VDPPM_ACTIVE_FLAG	RC	1b0	DPPM Flag 1b0 = DPPM operation not detected 1b1 = DPPM operation detected
2	VINDPM_ACTIVE_FLAG	RC	1b0	VINDPM Flag 1b0 = VINDPM operation not detected 1b1 = VIINDPM operation detected
1	THERMREG_ACTIVE_FLAG	RC	1b0	Thermal Regulation Flag 1b0 = Thermal Regulation not detected 1b1 = Thermal Regulation detected
0	VIN_PGOOD_FLAG	RC	1b0	VIN Power Good Flag 1b0 = No change in VIN Power Good Status 1b1 = Change in VIN Power Good Status detected.

9.5.1.5 FLAG1 Register (Address = 0x4) [reset = 0x0]

FLAG1 is shown in Figure 9-20 and described in Table 9-14.

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Clear on Read

Figure 9-20 FLAG1 Register

7	6	5	4	3	2	1	0
VIN_OVP_FAULT_FLAG	RESERVED	BAT_OCP_FAULT_FLAG	BAT_UVLO_FAULT_FLAG	TS_COLD_FLAG	TS_COOL_FLAG	TS_WARM_FLAG	TS_HOT_FLAG
RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0

Table 9-14 FLAG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VIN_OVP_FAULT_FLAG	RC	1b0	VIN Over Voltage Fault Flag 1b0 = No overvoltage condition detected 1b1 = VIN overvoltage condition detected
6	RESERVED	RC	1b0	Reserved
5	BAT_OCP_FAULT_FLAG	RC	1b0	Battery Over Current Protection Flag 1b0 = No Battery Over Current condition detected 1b1 = Battery Over Current condition detected
4	BAT_UVLO_FAULT_FLAG	RC	1b0	Battery Under Voltage Flag 1b0 = Battery below BATUVLO condition detected 1b1 = No Battery below BATUVLO condition detected
3	TS_COLD_FLAG	RC	1b0	TS Cold Region Entry Flag 1b0 = TS Cold Region Entry not detected 1b1 = TS Cold Region Entry detected
2	TS_COOL_FLAG	RC	1b0	TS Cool Region Entry Flag 1b0 = TS Cool Region Entry not detected 1b1 = TS Co0l Region Entry detected
1	TS_WARM_FLAG	RC	1b0	TS Warm Region Entry Flag 1b0 = TS Warm Region Entry not detected 1b1 = TS Warm Region Entry detected
0	TS_HOT_FLAG	RC	1b0	TS Hot Region Entry Flag 1b0 = TS Hot Region Entry not detected 1b1 = TS Hot Region Entry detected

9.5.1.6 FLAG2 Register (Address = 0x5) [reset = 0x0]

FLAG2 is shown in Figure 9-21 and described in Table 9-15.

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Clear on Read

Figure 9-21 FLAG2 Register

7	6	5	4	3	2	1	0
ADC_READY_FLAG	COMP1_ALARM_FLAG	COMP2_ALARM_FLAG	COMP3_ALARM_FLAG	RESERVED			TS_OPEN_FLAG
RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-3b000			RC-1b0

Table 9-15 FLAG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_READY_FLAG	RC	1b0	ADC Ready Flag 1b0 = No ADC conversion completed since last flag read 1b1 = ADC Conversion Completed
6	COMP1_ALARM_FLAG	RC	1b0	ADC COMP1 Threshold Flag 1b0 = No threshold crossing detected 1b1 = Selected ADC measurement crossed condition set by 1_ADCALARM_ABOVE bit
5	COMP2_ALARM_FLAG	RC	1b0	ADC COMP2 Threshold Flag 1b0 = No threshold crossing detected 1b1 = Selected ADC measurement crossed condition set by 2_ADCALARM_ABOVE bit
4	COMP3_ALARM_FLAG	RC	1b0	ADC COMP3 Threshold Flag 1b0 = No threshold crossing detected 1b1 = Selected ADC measurement crossed condition set by 3_ADCALARM_ABOVE bit
3-1	RESERVED	RC	3b000	Reserved
0	TS_OPEN_FLAG	RC	1b0	TS Open Flag 1b0 = No TS Open fault detected 1b1 = TS Open fault detected

9.5.1.7 FLAG3 Register (Address = 0x6) [reset = 0x0]

FLAG3 is shown in Figure 9-22 and described in Table 9-16.

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Clear on Read

Figure 9-22 FLAG3 Register

7	6	5	4	3	2	1	0
RESERVED	WD_FAULT_FLAG	SAFETY_TMR_FAULT_FLAG	LDO_OCP_FAULT_FLAG	RESERVED	MRWAKE1_TIMEOUT_FLAG	MRWAKE2_TIMEOUT_FLAG	MRRESET_WARN_FLAG
RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0	RC-1b0

Table 9-16 FLAG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	RC	1b0	Reserved
6	WD_FAULT_FLAG	RC	1b0	Watchdog Fault Flag 1b0 = Watchdog Timer not expired 1b1 = Watchdog Timer expired
5	SAFETY_TMR_FAULT_FLAG	RC	1b0	Safety Timer Fault Flag 1b0 = Safety Timer not expired 1b1 = Safety Timer Expired
4	LDO_OCP_FAULT_FLAG	RC	1b0	LDO Over Current Fault 1b0 = LDO Normal 1b1 = LDO Over current fault detected
3	Reserved	RC		Reserved
2	MRWAKE1_TIMEOUT_FLAG	RC	1b0	MR Wake 1 Timer Flag 1b0 = MR Wake 1 timer not expired 1b1 = MR Wake 1 timer expired
1	MRWAKE2_TIMEOUT_FLAG	RC	1b0	MR Wake 2 Timer Flag 1b0 = MR Wake 2 timer not expired 1b1 = MR Wake 2 timer expired
0	MRRESET_WARN_FLAG	RC	1b0	MR Reset Warn Timer Flag 1b0 = MR Reset Warn timer not expired 1b1 = MR Reset Warn timer expired

9.5.1.8 MASK0 Register (Address = 0x7) [reset = 0x0]

MASK0 is shown in Figure 9-23 and described in Table 9-17.

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Figure 9-23 MASK0 Register

7	6	5	4	3	2	1	0
RESERVED	CHRG_CV_MASK	CHARGE_DONE_MASK	IINLIM_ACTIVE_MASK	VDPPM_ACTIVE_MASK	VINDPM_ACTIVE_MASK	THERMREG_ACTIVE_MASK	VIN_PGOOD_MASK
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 9-17 MASK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	1b0	Reserved 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
6	CHRG_CV_MASK	R/W	1b0	Mask for CHRG_CV interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
5	CHARGE_DONE_MASK	R/W	1b0	Mask for CHARGE_DONE interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
4	IINLIM_ACTIVE_MASK	R/W	1b0	Mask for IINLIM_ACTIVE interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
3	VDPPM_ACTIVE_MASK	R/W	1b0	Mask for VDPPM_ACTIVE interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
2	VINDPM_ACTIVE_MASK	R/W	1b0	Mask for VINDPM_ACTIVE interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
1	THERMREG_ACTIVE_MASK	R/W	1b0	Mask for THERMREG_ACTIVE interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
0	VIN_PGOOD_MASK	R/W	1b0	Mask for VIN_PGOOD interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked

9.5.1.9 MASK1 Register (Address = 0x8) [reset = 0x0]

MASK1 is shown in Figure 9-24 and described in Table 9-18.

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Figure 9-24 MASK1 Register

7	6	5	4	3	2	1	0
VIN_OVP_FAULT_MASK	RESERVED	BAT_OCP_FAULT_MASK	BAT_UVLO_FAULT_MASK	TS_COLD_MASK	TS_COOL_MASK	TS_WARM_MASK	TS_HOT_MASK
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 9-18 MASK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VIN_OVP_FAULT_MASK	R/W	1b0	Mask for VIN_OVP_FAULT interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
6	RESERVED	R/W	1b0	Reserved
5	BAT_OCP_FAULT_MASK	R/W	1b0	Mask for BAT_OCP_FAULT interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
4	BAT_UVLO_FAULT_MASK	R/W	1b0	Mask for BAT_UVLO_FAULT interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
3	TS_COLD_MASK	R/W	1b0	Mask for TS_COLD interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
2	TS_COOL_MASK	R/W	1b0	Mask for TS_COOL interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
1	TS_WARM_MASK	R/W	1b0	Mask for TS_WARM interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
0	TS_HOT_MASK	R/W	1b0	Mask for TS_HOT interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked

9.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]

MASK2 is shown in Figure 9-25 and described in Table 9-19.

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Figure 9-25 MASK2 Register

7	6	5	4	3	2	1	0
ADC_READY_FLAG	COMP1_ALARM_FLAG	COMP2_ALARM_FLAG	COMP3_ALARM_FLAG	RESERVED			TS_OPEN_MASK
R/W-1b0	R/W-1b1	R/W-1b1	R/W-1b1	R/W-3b000			R/W-1b1

Table 9-19 MASK2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_READY_MASK	R/W	1b0	Mask for ADC_READY Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
6	COMP1_ALARM_MASK	R/W	1b1	Mask for COMP1_ALARM Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
5	COMP2_ALARM_MASK	R/W	1b1	Mask for COMP2_ALARM Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
4	COMP3_ALARM_MASK	R/W	1b1	Mask for COMP3_ALARM Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
3-1	RESERVED	R/W	3b000	Reserved
0	TS_OPEN_MASK	R/W	1b1	Mask for TS_OPEN Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked

9.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]

MASK3 is shown in Figure 9-26 and described in Table 9-20.

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Figure 9-26 MASK3 Register

7	6	5	4	3	2	1	0
RESERVED	WD_FAULT_MASK	SAFETY_TMR_FAULT_MASK	LDO_OCP_FAULT_MASK	RESERVED	MRWAKE1_TIMEOUT_MASK	MRWAKE2_TIMEOUT_MASK	MRRESET_WARN_MASK
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 9-20 MASK3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	1b0	Reserved
6	WD_FAULT_MASK	R/W	1b0	Mask for WD_FAULT Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
5	SAFETY_TMR_FAULT_MASK	R/W	1b0	Mask for SAFETY_TIMER_FAULT Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
4	LDO_OCP_FAULT_MASK	R/W	1b0	Mask for LDO_OCP_FAULT Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
3	RESERVED	R/W	1b0	Reserved
2	MRWAKE1_TIMEOUT_MASK	R/W	1b0	Mask for MRWAKE1_TIMEOUT Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
1	MRWAKE2_TIMEOUT_MASK	R/W	1b0	Mask for MRWAKE2_TIMEOUT Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked
0	MRRESET_WARN_MASK	R/W	1b0	Mask for MRRESET_WARN Interrupt 1b0 = Interrupt Not Masked 1b1 = Interrupt Masked

9.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]

VBAT_CTRL is shown in Figure 9-27 and described in Table 9-21.

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Figure 9-27 VBAT_CTRL Register

7	6	5	4	3	2	1	0
RESERVED	VBAT_REG_6:0
R/W-1b0	R/W-7b0111100

Table 9-21 VBAT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	1b0	Reserved
6-0	VBAT_REG_6:0	R/W	7b0111100	Battery Regulation Voltage (4.2 V default) VBATREG = 3.6 V + VBAT_REG code x 10 mV If a value greater than 4.6 V is written, the setting will go to 4.6 V

9.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]

ICHG_CTRL is shown in Figure 9-28 and described in Table 9-22.

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Figure 9-28 ICHG_CTRL Register

7	6	5	4	3	2	1	0
ICHG_7:0
R/W-8b00001000

Table 9-22 ICHG_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ICHG_7:0	R/W	8b00001000	Fast Charge Current (10 mA default) Fast Charge Current = 1.25 mA x ICHG code (ICHARGE_RANGE = 0) Fast Charge Current = 2.5 mA x ICHG code (ICHARGE_RANGE = 1)

9.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]

PCHRGCTRL is shown in Figure 9-29 and described in Table 9-23.

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Figure 9-29 PCHRGCTRL Register

7	6	5	4	3	2	1	0
ICHARGE_RANGE	RESERVED		IPRECHG_4:0
R/W-1b0	R/W-2b00		R/W-5b00010

Table 9-23 PCHRGCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ICHARGE_RANGE	R/W	1b0	Charge Current Step 1b0 = 1.25 mA step (318.75 mA max charge current) 1b1 = 2.5 mA step (500 mA max charge current)
6-5	RESERVED	R/W	2b00	Reserved
4-0	IPRECHG_4:0	R/W	5b00010	Pre-Charge Current (2.5 mA default) Pre-Charge Current = 1.25 mA x IPRECHG code (ICHARGE_RANGE = 0) Pre-Charge Current = 2.5 mA x IPRECHG code (ICHARGE_RANGE = 1)

Bit

Field

Type

Reset

Description

7

ICHARGE_RANGE

R/W

1b0

Charge Current Step

1b0 = 1.25 mA step (318.75 mA max charge current)

1b1 = 2.5 mA step (500 mA max charge current)

6-5

RESERVED

R/W

2b00

Reserved

4-0

IPRECHG_4:0

R/W

5b00010

Pre-Charge Current (2.5 mA default)
Pre-Charge Current = 1.25 mA x IPRECHG code (ICHARGE_RANGE = 0)
Pre-Charge Current = 2.5 mA x IPRECHG code (ICHARGE_RANGE = 1)

9.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]

TERMCTRL is shown in Figure 9-30 and described in Table 9-24.

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Figure 9-30 TERMCTRL Register

7	6	5	4	3	2	1	0
RESERVED		ITERM_4:0					TERM_DISABLE
R/W-2b00		R/W-5b01010					R/W-1b0

Table 9-24 TERMCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

2b00

Reserved

5-1

ITERM_4:0

R/W

5b01010

Termination Current (10% of ICHRG default)
Programmable Range = 1% to 31% of ICHRG

5b00000 = Do not Use

5b00001 = 1% of ICHRG

5b00010 = 2% of ICHRG

5b00100 = 4% of ICHRG

5b01000 = 8% of ICHRG

5b10000 = 16% of ICHRG

0

TERM_DISABLE

R/W

1b0

Termination Disable

1b0 = Termination Enabled

1b1 = Termination Disabled

9.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]

BUVLO is shown in Figure 9-31 and described in Table 9-25.

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Figure 9-31 BUVLO Register

7	6	5	4	3	2	1	0
RESERVED		VLOWV_SEL	IBAT_OCP_ILIM_1:0		BUVLO_2:0
R/W-2b00		R/W-1b0	R/W-2b00		R/W-3b000

Table 9-25 BUVLO Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	2b00	Reserved
5	VLOWV_SEL	R/W	1b0	Pre-charge to Fast Charge Threshold 1b0 = 3.0 V 1b1 = 2.8 V
4-3	IBAT_OCP_ILIM_1:0	R/W	2b00	Battery Over-Current Protection Threshold 2b00 = 1200 mA 2b01 = 1500 mA 2b10 = Disabled 2b11 = Disabled
2-0	BUVLO_2:0	R/W	3b000	Battery UVLO Voltage 3b000 = 3.0 V 3b001 = 3.0 V 3b010 = 3.0 V 3b011 = 2.8 V 3b100 = 2.6 V 3b101 = 2.4 V 3b110 = 2.2 V 3b111 = Disabled

9.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]

CHARGERCTRL0 is shown in Figure 9-32 and described in Table 9-26.

Return to Summary Table.

Figure 9-32 CHARGERCTRL0 Register

7	6	5	4	3	2	1	0
TS_EN	TS_CONTROL_MODE	VRH_THRESH	WATCHDOG_DISABLE	2XTMR_EN	SAFETY_TIMER_LIMIT_1:0		RESERVED
R/W-1b1	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-2b01		R/W-1b0

Table 9-26 CHARGERCTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TS_EN	R/W	1b1	TS Function Enable 1b0 = TS function disabled (Only charge control is disabled. TS_OPEN detection and TS ADC monitoring remain enabled) 1b1 = TS function enabled
6	TS_CONTROL_MODE	R/W	1b0	TS Function Control Mode 1b0 = Custom (JEITA) 1b1 = Disable charging on HOT/COLD Only
5	VRH_THRESH	R/W	1b0	Recharge Voltage Threshold 1b0 = 140 mV 1b1 = 200 mV
4	WATCHDOG_DISABLE	R/W	1b0	Watchdog Timer Disable 1b0 = Watchdog timer enabled 1b1 = Watchdog timer disabled
3	2XTMR_EN	R/W	1b0	Enable 2X Safety Timer 1b0 = The timer is not slowed at any time 1b1 = The timer is slowed by 2x when in any control other than CC or CV
2-1	SAFETY_TIMER_LIMIT_1:0	R/W	2b01	Charger Safety Timer 2b00 = 3 Hr Fast Charge 2b01 = 6 Hr Fast Charge 2b10 = 12 Hr Fast Charge 2b11 = Disabled
0	RESERVED	R/W	1b0	Reserved

9.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0x02]

CHARGERCTRL1 is shown in Figure 9-33 and described in Table 9-27.

Return to Summary Table.

Figure 9-33 CHARGERCTRL1 Register

7	6	5	4	3	2	1	0
VINDPM_DIS	VINPDM_2:0			DPPM_DIS	THERM_REG_2:0
R/W-1b0	R/W-3b000			R/W-1b0	R/W-3b010

Table 9-27 CHARGERCTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VINDPM_DIS	R/W	1b0	Disable VINDPM Function 1b0 = VINDPM Enabled 1b1 = VINDPM Disabled
6-4	VINPDM_2:0	R/W	3b000	VINDPM Level Selection 3b000 = 4.2 V 3b001 = 4.3 V 3b010 = 4.4 V 3b011 = 4.5 V 3b100 = 4.6 V 3b101 = 4.7 V 3b110 = 4.8 V 3b111 = 4.9 V
3	DPPM_DIS	R/W	1b0	DPPM Disable 1b0 = DPPM function enabled 1b1 = DPPM function disabled
2-0	THERM_REG_2:0	R/W	3b010	Thermal Charge Current Foldback Threshold 3b000 = 80°C 3b001 = 85°C 3b010 = 90°C 3b011 = 95°C 3b100 = 100°C 3b101 = 105°C 3b110 = 110°C 3b111 = Disabled

9.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x6]

ILIMCTRL is shown in Figure 9-34 and described in Table 9-28.

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Figure 9-34 ILIMCTRL Register

7	6	5	4	3	2	1	0
RESERVED					ILIM_2:0
R/W-5b00000					R/W-3b001

Table 9-28 ILIMCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	5b00000	Reserved
2-0	ILIM_2:0	R/W	3b001	Input Current Limit Level Selection 3b000 = 50 mA 3b001 = 100 mA 3b010 = 150 mA 3b011 = 200 mA 3b100 = 300 mA 3b101 = 400 mA 3b110 = 500 mA 3b111 = 600 mA

Bit

Field

Type

Reset

Description

7-3

RESERVED

R/W

5b00000

Reserved

2-0

ILIM_2:0

R/W

3b001

Input Current Limit Level Selection

3b000 = 50 mA

3b001 = 100 mA

3b010 = 150 mA

3b011 = 200 mA

3b100 = 300 mA

3b101 = 400 mA

3b110 = 500 mA

3b111 = 600 mA

9.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]

LDOCTRL is shown in Figure 9-35 and described in Table 9-29.

Return to Summary Table.

Figure 9-35 LDOCTRL Register

7	6	5	4	3	2	1	0
EN_LS_LDO	VLDO_4:0					LDO_SWITCH_CONFG	RESERVED
R/W-1b1	R/W-5b01100					R/W-1b0	R/W-1b0

Table 9-29 LDOCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EN_LS_LDO	R/W	1b1	LS/LDO Enable 1b0 = Disable LS/LDO 1b1 = Enable LS/LDO
6-2	VLDO_4:0	R/W	5b01100	LDO output voltage setting (1.8 V default) LDO Voltage = 600 mV + VLDO Code x 100 mV
1	LDO_SWITCH_CONFG	R/W	1b0	LDO / Load Switch Configuration Select 1b0 = LDO 1b1 = Load Switch
0	RESERVED	R/W	1b0	Reserved

9.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]

MRCTRL is shown in Figure 9-36 and described in Table 9-30.

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Figure 9-36 MRCTRL Register

7	6	5	4	3	2	1	0
MR_RESET_VIN	MR_WAKE1_TIMER	MR_WAKE2_TIMER	MR_RESET_WARN_1:0		MR_HW_RESET_1:0		RESERVED
R/W-1b0	R/W-1b0	R/W-1b1	R/W-2b01		R/W-2b01		R/W-1b0

Table 9-30 MRCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_RESET_VIN	R/W	1b0	VIN Power Good gated MR Reset Enable 1b0 = Reset sent when /MR reset time is met regardless of VIN state 1b1 = Reset sent when MR reset is met and Vin is valid
6	MR_WAKE1_TIMER	R/W	1b0	Wake 1 Timer setting 1b0 = 125 ms 1b1 = 500 ms
5	MR_WAKE2_TIMER	R/W	1b1	Wake 2 Timer setting 1b0 = 1 s 1b1 = 2 s
4-3	MR_RESET_WARN_1:0	R/W	2b01	MR Reset Warn Timer setting 2b00 = MR_HW_RESET - 0.5 s 2b01 = MR_HW_RESET - 1.0 s 2b10 = MR_HW_RESET - 1.5 s 2b11 = MR_HW_RESET - 2.0 s
2-1	MR_HW_RESET_1:0	R/W	2b01	MR HW Reset Timer setting 2b00 = 4 s 2b01 = 8 s 2b10 = 10 s 2b11 = 14 s
0	RESERVED	R/W	1b0	Reserved

9.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]

ICCTRL0 is shown in Figure 9-37 and described in Table 9-31.

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Figure 9-37 ICCTRL0 Register

7	6	5	4	3	2	1	0
EN_SHIP_MODE	RESERVED	AUTOWAKE_1:0		RESERVED	GLOBAL_INT_MASK	HW_RESET	SW_RESET
R/W-1b0	R/W-1b0	R/W-2b01		R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 9-31 ICCTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EN_SHIP_MODE	R/W	1b0	Ship Mode Enable 1b0 = Normal operation 1b1 = Enter Ship Mode when VIN is not valid and /MR is high
6	RESERVED	R/W	1b0	Reserved
5-4	AUTOWAKE_1:0	R/W	2b01	Auto-wakeup Timer (TRESTART) for /MR HW Reset 2b00 = 0.6 s 2b01 = 1.2 s 2b10 = 2.4 s 2b11 = 5 s
3	RESERVED	R/W	1b0	Reserved
2	GLOBAL_INT_MASK	R/W	1b0	Global Interrupt Mask 1b0 = Normal Operation 1b1 = Mask all interrupts
1	HW_RESET	R/W	1b0	HW Reset 1b0 = Normal operation 1b1 = HW Reset. Temporarily power down all power rails, except VDD. I²C Register go to default settings.
0	SW_RESET	R/W	1b0	SW_Reset 1b0 = Normal operation 1b1 = SW Reset. I²C Registers go to default settings.

9.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]

ICCTRL1 is shown in Figure 9-38 and described in Table 9-32.

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Figure 9-38 ICCTRL1 Register

7	6	5	4	3	2	1	0
MR_LPRESS_ACTION_1:0		ADCIN_MODE	RESERVED	PG_MODE_1:0		PMID_MODE_1:0
R/W-2b00		R/W-1b0	R/W-1b0	R/W-2b00		R/W-2b00

Table 9-32 ICCTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	MR_LPRESS_ACTION_1:0	R/W	2b00	MR Long Press Action 2b00 = HW Reset (Power Cycle) 2b01 = Do nothing 2b10 = Enter Ship Mode 2b11 = Enter Ship Mode
5	ADCIN_MODE	R/W	1b0	ADCIN Pin Mode of Operation 1b0 = General Purpose ADC input (no Internal biasing) 1b1 = 10K NTC ADC input (80 µA biasing)
4	RESERVED	R/W	1b0	Reserved
3-2	PG_MODE_1:0	R/W	2b00	PG Pin Mode of Operation 2b00 = VIN Power Good 2b01 = Deglitched Level Shifted /MR 2b10 = General Purpose Open Drain Output 2b11 = General Purpose Open Drain Output
1-0	PMID_MODE_1:0	R/W	2b00	PMID Control Sets how PMID is powered in any state, except Ship Mode. 2b00 = PMID powered from BAT or VIN if present 2b01 = PMID powered from BAT only, even if VIN is present 2b10 = PMID disconnected and left floating 2b11 = PMID disconnected and pulled down.

9.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]

ICCTRL2 is shown in Figure 9-39 and described in Table 9-33.

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Figure 9-39 ICCTRL2 Register

7	6	5	4	3	2	1	0
RESERVED			GPO_PG	RESERVED		HWRESET_14S_WD	CHARGER_DISABLE
R/W-3b010			R/W-1b0	R/W-2b00		R/W-1b0	R/W-1b0

Table 9-33 ICCTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	3b010	Reserved
4	GPO_PG	R/W	1b0	/PG General Purpose Output State Control 1b0 = Pulled Down 1b1 = High Z
3-2	RESERVED	R/W	2b00	Reserved
1	HWRESET_14S_WD	R/W	1b0	Enable for 14-second I²C watchdog timer for HW Reset after VIN connection 1b0 = Timer disabled 1b1 = Device will perform HW reset if no I²C transaction is done within 14 s after VIN is present
0	CHARGER_DISABLE	R/W	1b0	Charge Disable 1b0 = Charge enabled if /CE pin is low 1b1 = Charge disabled

9.5.1.25 ADCCTRL0 Register (Address = 0x40) [reset = 0x2]

ADCCTRL0 is shown in Figure 9-40 and described in Table 9-34.

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Figure 9-40 ADCCTRL0 Register

7	6	5	4	3	2	1	0
ADC_READ_RATE_1:0		ADC_CONV_START	ADC_CONV_SPEED_1:0		ADC_COMP1_2:0
R/W-2b00		R/W-1b0	R/W-2b00		R/W-3b010

Table 9-34 ADCCTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	ADC_READ_RATE_1:0	R/W	2b00	Read rate for ADC measurements in BAT Only operation 2b00 = Manual Read (Measurement done when ADC_CONV_START is set) 2b01 = Continuous 2b10 = Every 1 second 2b11 = Every 1 minute
5	ADC_CONV_START	R/W	1b0	ADC Conversion Start Trigger Bit goes back to 0 when conversion is complete 1b0 = No ADC conversion 1b1 = Initiates ADC measurement in Manual Read operation
4-3	ADC_CONV_SPEED_1:0	R/W	2b00	ADC Conversion Speed 2b00 = 24 ms (highest accuracy) 2b01 = 12 ms 2b10 = 6 ms 2b11 = 3 ms
2-0	ADC_COMP1_2:0	R/W	3b010	ADC Channel for Comparator 1 3b000 = Disabled 3b001 = ADCIN 3b010 = TS 3b011 = VBAT 3b100 = ICHARGE 3b101 = VIN 3b110 = PMID 3b111 = IIN

9.5.1.26 ADCCTRL1 Register (Address = 0x41) [reset = 0x40]

ADCCTRL1 is shown in Figure 9-41 and described in Table 9-35.

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Figure 9-41 ADCCTRL1 Register

7	6	5	4	3	2	1	0
ADC_COMP2_2:0			ADC_COMP3_2:0			RESERVED
R/W-3b010			R/W-3b000			R/W-2b00

Table 9-35 ADCCTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

ADC_COMP2_2:0

R/W

3b010

ADC Channel for Comparator 2

3b000 = Disabled

3b001 = ADCIN

3b010 = TS

3b011 = VBAT

3b100 = ICHARGE

3b101 = VIN

3b110 = PMID

3b111 = IIN

4-2

ADC_COMP3_2:0

R/W

3b000

ADC Channel for Comparator 3

3b000 = Disabled

3b001 = ADCIN

3b010 = TS

3b011 = VBAT

3b100 = ICHARGE

3b101 = VIN

3b110 = PMID

3b111 = IIN

1-0

RESERVED

R/W

2b00

Reserved

9.5.1.27 ADC_DATA_VBAT_M Register (Address = 0x42) [reset = X]

ADC_DATA_VBAT_M is shown in Figure 9-42 and described in Table 9-36.

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Figure 9-42 ADC_DATA_VBAT_M Register

7	6	5	4	3	2	1	0
VBAT_ADC_15:8
R-X

Table 9-36 ADC_DATA_VBAT_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VBAT_ADC_15:8	R	X	ADC VBAT Measurement MSB

9.5.1.28 ADC_DATA_VBAT_L Register (Address = 0x43) [reset = X]

ADC_DATA_VBAT_L is shown in Figure 9-43 and described in Table 9-37.

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Figure 9-43 ADC_DATA_VBAT_L Register

7	6	5	4	3	2	1	0
VBAT_ADC_7:0
R-X

Table 9-37 ADC_DATA_VBAT_L Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VBAT_ADC_7:0	R	X	ADC VBAT Measurement LSB

9.5.1.29 ADC_DATA_TS_M Register (Address = 0x44) [reset = X]

ADC_DATA_TS_M is shown in Figure 9-44 and described in Table 9-38.

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Figure 9-44 ADC_DATA_TS_M Register

7	6	5	4	3	2	1	0
TS_ADC_15:8
R-X

Table 9-38 ADC_DATA_TS_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	TS_ADC_15:8	R	X	ADC TS Measurement MSB

9.5.1.30 ADC_DATA_TS_L Register (Address = 0x45) [reset = X]

ADC_DATA_TS_L is shown in Figure 9-45 and described in Table 9-39.

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Figure 9-45 ADC_DATA_TS_L Register

7	6	5	4	3	2	1	0
TS_ADC_7:0
R-X

Table 9-39 ADC_DATA_TS_L Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	TS_ADC_7:0	R	X	ADC TS Measurement LSB

9.5.1.31 ADC_DATA_ICHG_M Register (Address = 0x46) [reset = X]

ADC_DATA_ICHG_M is shown in Figure 9-46 and described in Table 9-40.

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Figure 9-46 ADC_DATA_ICHG_M Register

7	6	5	4	3	2	1	0
ICHG_ADC_15:8
R-X

Table 9-40 ADC_DATA_ICHG_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ICHG_ADC_15:8	R	X	ADC ICHG Measurement MSB

9.5.1.32 ADC_DATA_ICHG_L Register (Address = 0x47) [reset = X]

ADC_DATA_ICHG_L is shown in Figure 9-47 and described in Table 9-41.

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Figure 9-47 ADC_DATA_ICHG_L Register

7	6	5	4	3	2	1	0
ICHG_ADC_7:0
R-X

Table 9-41 ADC_DATA_ICHG_L Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ICHG_ADC_7:0	R	X	ADC ICHG Measurement LSB

9.5.1.33 ADC_DATA_ADCIN_M Register (Address = 0x48) [reset = X]

ADC_DATA_ADCIN_M is shown in Figure 9-48 and described in Table 9-42.

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Figure 9-48 ADC_DATA_ADCIN_M Register

7	6	5	4	3	2	1	0
ADCIN_ADC_15:8
R-X

Table 9-42 ADC_DATA_ADCIN_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADCIN_ADC_15:8	R	X	ADC ADCIN Measurement MSB

9.5.1.34 ADC_DATA_ADCIN_L Register (Address = 0x49) [reset = X]

ADC_DATA_ADCIN_L is shown in Figure 9-49 and described in Table 9-43.

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Figure 9-49 ADC_DATA_ADCIN_L Register

7	6	5	4	3	2	1	0
ADCIN_ADC_7:0
R-X

Table 9-43 ADC_DATA_ADCIN_L Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADCIN_ADC_7:0	R	X	ADC ADCIN Measurement LSB

9.5.1.35 ADC_DATA_VIN_M Register (Address = 0x4A) [reset = X]

ADC_DATA_VIN_M is shown in Figure 9-50 and described in Table 9-44.

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Figure 9-50 ADC_DATA_VIN_M Register

7	6	5	4	3	2	1	0
VIN_ADC_15:8
R-X

Table 9-44 ADC_DATA_VIN_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VIN_ADC_15:8	R	X	ADC VIN Measurement MSB

9.5.1.36 ADC_DATA_VIN_L Register (Address = 0x4B) [reset = X]

ADC_DATA_VIN_L is shown in Figure 9-51 and described in Table 9-45.

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Figure 9-51 ADC_DATA_VIN_L Register

7	6	5	4	3	2	1	0
VIN_ADC_7:0
R-X

Table 9-45 ADC_DATA_VIN_L Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VIN_ADC_7:0	R	X	ADC VIN Measurement LSB

9.5.1.37 ADC_DATA_PMID_M Register (Address = 0x4C) [reset = X]

ADC_DATA_PMID_M is shown in Figure 9-52 and described in Table 9-46.

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Figure 9-52 ADC_DATA_PMID_M Register

7	6	5	4	3	2	1	0
PMID_ADC_15:8
R-X

Table 9-46 ADC_DATA_PMID_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PMID_ADC_15:8	R	X	ADC PMID Measurement MSB

9.5.1.38 ADC_DATA_PMID_L Register (Address = 0x4D) [reset = X]

ADC_DATA_PMID_L is shown in Figure 9-53 and described in Table 9-47.

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Figure 9-53 ADC_DATA_PMID_L Register

7	6	5	4	3	2	1	0
PMID_ADC_7:0
R-X

Table 9-47 ADC_DATA_PMID_L Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PMID_ADC_7:0	R	X	ADC PMID Measurement LSB

9.5.1.39 ADC_DATA_IIN_M Register (Address = 0x4E) [reset = X]

ADC_DATA_IIN_M is shown in Figure 9-54 and described in Table 9-48.

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Figure 9-54 ADC_DATA_IIN_M Register

7	6	5	4	3	2	1	0
IIN_ADC_15:8
R-X

Table 9-48 ADC_DATA_IIN_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	IIN_ADC_15:8	R	X	ADC IIN Measurement MSB

9.5.1.40 ADC_DATA_IIN_L Register (Address = 0x4F) [reset = X]

ADC_DATA_IIN_L is shown in Figure 9-55 and described in Table 9-49.

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Figure 9-55 ADC_DATA_IIN_L Register

7	6	5	4	3	2	1	0
IIN_ADC_7:0
R-X

Table 9-49 ADC_DATA_IIN_L Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	IIN_ADC_7:0	R	X	ADC IIN Measurement LSB

9.5.1.41 ADCALARM_COMP1_M Register (Address = 0x52) [reset = 0x23]

ADCALARM_COMP1_M is shown in Figure 9-56 and described in Table 9-50.

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Figure 9-56 ADCALARM_COMP1_M Register

7	6	5	4	3	2	1	0
1_ADCALARM_15:8
R/W-8b00100011

Table 9-50 ADCALARM_COMP1_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	1_ADCALARM_15:8	R/W	8b00100011	ADC Comparator 1 Threshold MSB

9.5.1.42 ADCALARM_COMP1_L Register (Address = 0x53) [reset = 0x20]

ADCALARM_COMP1_L is shown in Figure 9-57 and described in Table 9-51.

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Figure 9-57 ADCALARM_COMP1_L Register

7	6	5	4	3	2	1	0
1_ADCALARM_7:4				1_ADCALARM_ABOVE	RESERVED
R/W-4b0010				R/W-1b0	R/W-3b000

Table 9-51 ADCALARM_COMP1_L Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

1_ADCALARM_7:4

R/W

4b0010

ADC Comparator 1 Threshold LSB

3

1_ADCALARM_ABOVE

R/W

1b0

ADC Comparator1 Polarity

1b0 = Set Flag and send interrupt if ADC measurement becomes lower than comparator threshold

1b1 = Set Flag and send interrupt if ADC measurement is becomes higher than comparator threshold

2-0

RESERVED

R/W

3b000

Reserved

9.5.1.43 ADCALARM_COMP2_M Register (Address = 0x54) [reset = 0x38]

ADCALARM_COMP2_M is shown in Figure 9-58 and described in Table 9-52.

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Figure 9-58 ADCALARM_COMP2_M Register

7	6	5	4	3	2	1	0
2_ADCALARM_15:8
R/W-8b00111000

Table 9-52 ADCALARM_COMP2_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	2_ADCALARM_15:8	R/W	8b00111000	ADC Comparator 2 Threshold MSB

9.5.1.44 ADCALARM_COMP2_L Register (Address = 0x55) [reset = 0x90]

ADCALARM_COMP2_L is shown in Figure 9-59 and described in Table 9-53.

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Figure 9-59 ADCALARM_COMP2_L Register

7	6	5	4	3	2	1	0
2_ADCALARM_7:4				2_ADCALARM_ABOVE	RESERVED
R/W-4b1001				R/W-1b0	R/W-3b000

Table 9-53 ADCALARM_COMP2_L Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

2_ADCALARM_7:4

R/W

4b1001

ADC Comparator 2 Threshold LSB

3

2_ADCALARM_ABOVE

R/W

1b0

ADC Comparator 2 Polarity

1b0 = Set Flag and send interrupt if ADC measurement becomes lower than comparator threshold

1b1 = Set Flag and send interrupt if ADC measurement is becomes higher than comparator threshold

2-0

RESERVED

R/W

3b000

Reserved

9.5.1.45 ADCALARM_COMP3_M Register (Address = 0x56) [reset = 0x0]

ADCALARM_COMP3_M is shown in Figure 9-60 and described in Table 9-54.

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Figure 9-60 ADCALARM_COMP3_M Register

7	6	5	4	3	2	1	0
3_ADCALARM_15:8
R/W-8b00000000

Table 9-54 ADCALARM_COMP3_M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	3_ADCALARM_15:8	R/W	8b00000000	ADC Comparator 3 Threshold MSB

9.5.1.46 ADCALARM_COMP3_L Register (Address = 0x57) [reset = 0x0]

ADCALARM_COMP3_L is shown in Figure 9-61 and described in Table 9-55.

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Figure 9-61 ADCALARM_COMP3_L Register

7	6	5	4	3	2	1	0
3_ADCALARM_7:4				3_ADCALARM_ABOVE	RESERVED
R/W-4b0000				R/W-1b0	R/W-3b000

Table 9-55 ADCALARM_COMP3_L Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3_ADCALARM_7:4

R/W

4b0000

ADC Comparator 3 Threshold LSB

3

3_ADCALARM_ABOVE

R/W

1b0

ADC Comparator 3 Polarity

1b0 = Set Flag and send interrupt if ADC measurement becomes lower than comparator threshold

1b1 = Set Flag and send interrupt if ADC measurement is becomes higher than comparator threshold

2-0

RESERVED

R/W

3b000

Reserved

9.5.1.47 ADC_READ_EN Register (Address = 0x58) [reset = 0x0]

ADC_READ_EN is shown in Figure 9-62 and described in Table 9-56.

Return to Summary Table.

Figure 9-62 ADC_READ_EN Register

7	6	5	4	3	2	1	0
EN_IIN_READ	EN_PMID_READ	EN_ICHG_READ	EN_VIN_READ	EN_VBAT_READ	EN_TS_READ	EN_ADCIN_READ	RESERVED
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 9-56 ADC_READ_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EN_IIN_READ	R/W	1b0	Enable measurement for Input Current (IIN) Channel 1b0 = ADC measurement disabled 1b1 = ADC measurement enabled
6	EN_PMID_READ	R/W	1b0	Enable measurement for PMID Channel 1b0 = ADC measurement disabled 1b1 = ADC measurement enabled
5	EN_ICHG_READ	R/W	1b0	Enable measurement for Charge Current Channel 1b0 = ADC measurement disabled 1b1 = ADC measurement enabled
4	EN_VIN_READ	R/W	1b0	Enable measurement for Input Voltage (VIN) Channel 1b0 = ADC measurement disabled 1b1 = ADC measurement enabled
3	EN_VBAT_READ	R/W	1b0	Enable measurement for Battery Voltage (VBAT) Channel 1b0 = ADC measurement disabled 1b1 = ADC measurement enabled
2	EN_TS_READ	R/W	1b0	Enable measurement for TS Channel 1b0 = ADC measurement disabled 1b1 = ADC measurement enabled
1	EN_ADCIN_READ	R/W	1b0	Enable measurement for ADCIN Channel 1b0 = ADC measurement disabled 1b1 = ADC measurement enabled
0	RESERVED	R/W	1b0	Reserved

9.5.1.48 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]

TS_FASTCHGCTRL is shown in Figure 9-63 and described in Table 9-57.

Return to Summary Table.

Figure 9-63 TS_FASTCHGCTRL Register

7	6	5	4	3	2	1	0
RESERVED	TS_VBAT_REG__2:0			RESERVED	TS_ICHRG_2:0
R/W-1b0	R/W-3b011			R/W-1b0	R/W-3b100

Table 9-57 TS_FASTCHGCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	1b0	Reserved
6-4	TS_VBAT_REG__2:0	R/W	3b011	Reduced target battery voltage during Warm 3b000 = No reduction 3b001 = VBAT_REG - 50 mV 3b010 = VBAT_REG - 100 mV 3b011 = VBAT_REG - 150 mV 3b100 = VBAT_REG - 200 mV 3b101 = VBAT_REG - 250 mV 3b110 = VBAT_REG - 300 mV 3b111 = VBAT_REG - 350 mV
3	RESERVED	R/W	1b0	Reserved
2-0	TS_ICHRG_2:0	R/W	3b100	Fast charge current when decreased by TS function 3b000 = No reduction 3b001 = 0.875 x ICHG 3b010 = 0.750 x ICHG 3b011 = 0.625 x ICHG 3b100 = 0.500 x ICHG 3b101 = 0.375 x ICHG 3b110 = 0.250 x ICHG 3b111 = 0.125 x ICHG

9.5.1.49 TS_COLD Register (Address = 0x62) [reset = 0x7C]

TS_COLD is shown in Figure 9-64 and described in Table 9-58.

Return to Summary Table.

Figure 9-64 TS_COLD Register

7	6	5	4	3	2	1	0
TS_COLD_7:0
R/W-8b01111100

Table 9-58 TS_COLD Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

TS_COLD_7:0

R/W

8b01111100

TS Cold Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.50 TS_COOL Register (Address = 0x63) [reset = 0x6D]

TS_COOL is shown in Figure 9-65 and described in Table 9-59.

Return to Summary Table.

Figure 9-65 TS_COOL Register

7	6	5	4	3	2	1	0
TS_COOL_7:0
R/W-8b01101101

Table 9-59 TS_COOL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

TS_COOL_7:0

R/W

8b01101101

TS Cool Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.51 TS_WARM Register (Address = 0x64) [reset = 0x38]

TS_WARM is shown in Figure 9-66 and described in Table 9-60.

Return to Summary Table.

Figure 9-66 TS_WARM Register

7	6	5	4	3	2	1	0
TS_WARM_7:0
R/W-8b00111000

Table 9-60 TS_WARM Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

TS_WARM_7:0

R/W

8b00111000

TS Warm Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.52 TS_HOT Register (Address = 0x65) [reset = 0x27]

TS_HOT is shown in Figure 9-67 and described in Table 9-61.

Return to Summary Table.

Figure 9-67 TS_HOT Register

7	6	5	4	3	2	1	0
TS_HOT_7:0
R/W-8b00100111

Table 9-61 TS_HOT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

TS_HOT_7:0

R/W

8b00100111

TS Hot Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.53 DEVICE_ID Register (Address = 0x6F) [reset = 0x3C]

DEVICE_ID is shown in Figure 9-68 and described in Table 9-62.

Return to Summary Table.

Figure 9-68 DEVICE_ID Register

7	6	5	4	3	2	1	0
DEVICE_ID_7:0
R-8b00111100

Table 9-62 DEVICE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DEVICE_ID_7:0	R	8b00111100	Device ID 111100b = BQ25157

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9.5.1 I2C Registers

9.5.1.1 STAT0 Register (Address = 0x0) [reset = X]

9.5.1.2 STAT1 Register (Address = 0x1) [reset = X]

9.5.1.3 STAT2 Register (Address = 0x2) [reset = X]

9.5.1.4 FLAG0 Register (Address = 0x3) [reset = 0x0]

9.5.1.5 FLAG1 Register (Address = 0x4) [reset = 0x0]

9.5.1.6 FLAG2 Register (Address = 0x5) [reset = 0x0]

9.5.1.7 FLAG3 Register (Address = 0x6) [reset = 0x0]

9.5.1.8 MASK0 Register (Address = 0x7) [reset = 0x0]

9.5.1.9 MASK1 Register (Address = 0x8) [reset = 0x0]

9.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]

9.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]

9.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]

9.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]

9.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]

9.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]

9.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]

9.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]

9.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0x02]

9.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x6]

9.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]

9.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]

9.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]

9.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]

9.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]

9.5.1.25 ADCCTRL0 Register (Address = 0x40) [reset = 0x2]

9.5.1.26 ADCCTRL1 Register (Address = 0x41) [reset = 0x40]

9.5.1.27 ADC_DATA_VBAT_M Register (Address = 0x42) [reset = X]

9.5.1.28 ADC_DATA_VBAT_L Register (Address = 0x43) [reset = X]

9.5.1.29 ADC_DATA_TS_M Register (Address = 0x44) [reset = X]

9.5.1.30 ADC_DATA_TS_L Register (Address = 0x45) [reset = X]

9.5.1.31 ADC_DATA_ICHG_M Register (Address = 0x46) [reset = X]

9.5.1.32 ADC_DATA_ICHG_L Register (Address = 0x47) [reset = X]

9.5.1.33 ADC_DATA_ADCIN_M Register (Address = 0x48) [reset = X]

9.5.1.34 ADC_DATA_ADCIN_L Register (Address = 0x49) [reset = X]

9.5.1.35 ADC_DATA_VIN_M Register (Address = 0x4A) [reset = X]

9.5.1.36 ADC_DATA_VIN_L Register (Address = 0x4B) [reset = X]

9.5.1.37 ADC_DATA_PMID_M Register (Address = 0x4C) [reset = X]

9.5.1.38 ADC_DATA_PMID_L Register (Address = 0x4D) [reset = X]

9.5.1.39 ADC_DATA_IIN_M Register (Address = 0x4E) [reset = X]

9.5.1.40 ADC_DATA_IIN_L Register (Address = 0x4F) [reset = X]

9.5.1.41 ADCALARM_COMP1_M Register (Address = 0x52) [reset = 0x23]

9.5.1.42 ADCALARM_COMP1_L Register (Address = 0x53) [reset = 0x20]

9.5.1.43 ADCALARM_COMP2_M Register (Address = 0x54) [reset = 0x38]

9.5.1.44 ADCALARM_COMP2_L Register (Address = 0x55) [reset = 0x90]

9.5.1.45 ADCALARM_COMP3_M Register (Address = 0x56) [reset = 0x0]

9.5.1.46 ADCALARM_COMP3_L Register (Address = 0x57) [reset = 0x0]

9.5.1.47 ADC_READ_EN Register (Address = 0x58) [reset = 0x0]

9.5.1.48 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]

9.5.1.49 TS_COLD Register (Address = 0x62) [reset = 0x7C]

9.5.1.50 TS_COOL Register (Address = 0x63) [reset = 0x6D]

9.5.1.51 TS_WARM Register (Address = 0x64) [reset = 0x38]

9.5.1.52 TS_HOT Register (Address = 0x65) [reset = 0x27]

9.5.1.53 DEVICE_ID Register (Address = 0x6F) [reset = 0x3C]

9.5.1 I²C Registers