The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 11-1) is important to prevent electrical and magnetic field radiation and high frequency resonant problems.

1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.
2. Put output capacitor near to the inductor and the IC.
3. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
4. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
5. It is OK to connect all grounds together to reduce PCB size and improve thermal dissipation.
6. Try to avoid ground planes in parallel with high frequency traces in other layers.

   See the EVM design for the recommended component placement with trace and via locations.