ZHCSGA3A march   2017  – march 2023 BQ25601

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset (POR)
      2. 9.3.2 Device Power Up from Battery without Input Source
      3. 9.3.3 Power Up from Input Source
        1. 9.3.3.1 Power Up REGN Regulation
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection
          1. 9.3.3.3.1 PSEL Pins Sets Input Current Limit in BQ25601
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Converter Power Up
      4. 9.3.4 Boost Mode Operation From Battery
      5. 9.3.5 Host Mode and Standalone Power Management
        1. 9.3.5.1 Host Mode and Default Mode in BQ25601
      6. 9.3.6 Power Path Management
      7. 9.3.7 Battery Charging Management
        1. 9.3.7.1 Autonomous Charging Cycle
        2. 9.3.7.2 Battery Charging Profile
        3. 9.3.7.3 Charging Termination
        4. 9.3.7.4 Thermistor Qualification
        5. 9.3.7.5 JEITA Guideline Compliance During Charging Mode
        6. 9.3.7.6 Boost Mode Thermistor Monitor During Battery Discharge Mode
        7. 9.3.7.7 Charging Safety Timer
      8. 9.3.8 Protections
        1. 9.3.8.1 Voltage and Current Monitoring in Converter Operation
          1. 9.3.8.1.1 Voltage and Current Monitoring in Buck Mode
            1. 9.3.8.1.1.1 Input Overvoltage (ACOV)
            2. 9.3.8.1.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.3.8.2 Voltage and Current Monitoring in Boost Mode
          1. 9.3.8.2.1 VBUS Soft Start
          2. 9.3.8.2.2 VBUS Output Protection
          3. 9.3.8.2.3 Boost Mode Overvoltage Protection
        3. 9.3.8.3 Thermal Regulation and Thermal Shutdown
          1. 9.3.8.3.1 Thermal Protection in Buck Mode
          2. 9.3.8.3.2 Thermal Protection in Boost Mode
        4. 9.3.8.4 Battery Protection
          1. 9.3.8.4.1 Battery Overvoltage Protection (BATOVP)
          2. 9.3.8.4.2 Battery Overdischarge Protection
          3. 9.3.8.4.3 System Overcurrent Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Narrow VDC Architecture
      2. 9.4.2 Dynamic Power Management
      3. 9.4.3 Supplement Mode
      4. 9.4.4 Shipping Mode and QON Pin
        1. 9.4.4.1 BATFET Disable Mode (Shipping Mode)
        2. 9.4.4.2 BATFET Enable (Exit Shipping Mode)
        3. 9.4.4.3 BATFET Full System Reset
        4. 9.4.4.4 QON Pin Operations
      5. 9.4.5 Status Outputs ( PG, STAT, INT )
        1. 9.4.5.1 Power Good Indicator ( PG Pin and PG_STAT Bit)
        2. 9.4.5.2 Charging Status Indicator (STAT)
        3. 9.4.5.3 Interrupt to Host ( INT)
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Data Validity
        2. 9.5.1.2 START and STOP Conditions
        3. 9.5.1.3 Byte Format
        4. 9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.5.1.5 Target Address and Data Direction Bit
        6. 9.5.1.6 Single Read and Write
        7. 9.5.1.7 Multi-Read and Multi-Write
    6. 9.6 Register Maps
      1. 9.6.1  REG00
      2. 9.6.2  REG01
      3. 9.6.3  REG02
      4. 9.6.4  REG03
      5. 9.6.5  REG04
      6. 9.6.6  REG05
      7. 9.6.7  REG06
      8. 9.6.8  REG07
      9. 9.6.9  REG08
      10. 9.6.10 REG09
      11. 9.6.11 REG0A
      12. 9.6.12 REG0B
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.4.4.4 QON Pin Operations

The QON pin incorporates two functions to control BATFET. QON is pulled up to VQON by an internal 200-kΩ pull-up resistor.

  1. BATFET Enable: A QON logic transition from high to low with longer than tSHIPMODE deglitch turns on BATFET to exit shipping mode. When exiting shipping mode, HIZ is enabled (EN_HIZ = 1) as well. HIZ can be disabled (EN_HIZ = 0) by the host after exiting shipping mode. OTG cannot be enabled (OTG_CONFIG = 1) until HIZ is disabled.
  2. BATFET Reset: When QON is driven to logic low by at least tQON_RST while adapter is not plugged in (and BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST. The BATFET is re-enabled after tBATFET_RST duration. This function allows systems connected to SYS to have power-on-reset. This function can be disabled by setting BATFET_RST_EN bit to 0.

Figure 9-10 shows the sample external configurations for each.

GUID-03B92F74-23F1-4187-A176-9825A737BA3B-low.gifFigure 9-10 QON Timing
GUID-41338888-B06E-40DA-86FC-12B4F8F5EA03-low.gifFigure 9-11 QON Circuit
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