ZHCSLT1B december   2020  – july 2023 BQ25672

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Device Power Up from Battery without Input Source
      4. 8.3.4  Device Power Up from Input Source
        1. 8.3.4.1 Power Up REGN LDO
        2. 8.3.4.2 Poor Source Qualification
        3. 8.3.4.3 ILIM_HIZ Pin
        4. 8.3.4.4 Default VINDPM Setting
        5. 8.3.4.5 Input Source Type Detection
          1. 8.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 8.3.4.5.2 HVDCP Detection Procedure
          3. 8.3.4.5.3 Connector Fault Detection
      5. 8.3.5  Dual-Input Power Mux
        1. 8.3.5.1 VBUS Input Only
        2. 8.3.5.2 One ACFET-RBFET
        3. 8.3.5.3 Two ACFETs-RBFETs
      6. 8.3.6  Buck Converter Operation
        1. 8.3.6.1 Force Input Current Limit Detection
        2. 8.3.6.2 Input Current Optimizer (ICO)
        3. 8.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 8.3.6.4 Pulse Frequency Modulation (PFM)
        5. 8.3.6.5 Device HIZ State
      7. 8.3.7  USB On-The-Go (OTG)
        1. 8.3.7.1 OTG Mode to Power External Devices
      8. 8.3.8  Power Path Management
        1. 8.3.8.1 Narrow Voltage DC Architecture
        2. 8.3.8.2 Dynamic Power Management
      9. 8.3.9  Battery Charging Management
        1. 8.3.9.1 Autonomous Charging Cycle
        2. 8.3.9.2 Battery Charging Profile
        3. 8.3.9.3 Charging Termination
        4. 8.3.9.4 Charging Safety Timer
        5. 8.3.9.5 Thermistor Qualification
          1. 8.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 8.3.10 Integrated 16-Bit ADC for Monitoring
      11. 8.3.11 Status Outputs ( STAT, and INT)
        1. 8.3.11.1 Charging Status Indicator (STAT Pin)
        2. 8.3.11.2 Interrupt to Host ( INT)
      12. 8.3.12 Ship FET Control
        1. 8.3.12.1 Shutdown Mode
        2. 8.3.12.2 Ship Mode
        3. 8.3.12.3 System Power Reset
      13. 8.3.13 Protections
        1. 8.3.13.1 Voltage and Current Monitoring
          1. 8.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 8.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 8.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 8.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 8.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 8.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 8.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 8.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 8.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 8.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 8.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 8.3.14 Serial Interface
        1. 8.3.14.1 Data Validity
        2. 8.3.14.2 START and STOP Conditions
        3. 8.3.14.3 Byte Format
        4. 8.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.14.5 Target Address and Data Direction Bit
        6. 8.3.14.6 Single Write and Read
        7. 8.3.14.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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订购信息

6 Pin Configuration and Functions

GUID-F6E592D8-85E0-4F52-A1F4-17DC13648CD0-low.gif Figure 6-1 RQM Package29-Pin VQFNTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
STAT 1 DO Open Drain Charge Status Output – It indicates various charger operations. Connect to the pull up rail via a 10kΩ resistor. LOW indicates charging in progress. HIGH indicates charging completed or charging disabled. When any fault condition occurs, STAT pin blinks at 1Hz. The STAT pin function can be disabled when DIS_STAT bit is set to 1.
VBUS 2-3 P Charger Input Voltage – The power input terminal of the charger. An input current sensing circuit is connected between VBUS and PMID. The recommended capacitors at VBUS are 2 pieces of 10μF and one piece of 0.1μF ceramic capacitors. Place the 0.1μF ceramic capacitor as close as possible to the charger IC.
BTST1 4 P Input High Side Power MOSFET Gate Driver Power Supply – Connect a 10V or higher rating, 47nF ceramic capacitor between SW1 and BTST1 as the bootstrap capacitor for driving high side switching MOSFET (Q1).
REGN 5 P The Charger Internal Linear Regulator Output – It is supplied from either VBUS or BAT dependent on which voltage is higher. Connect a 10V, 4.7μF ceramic capacitor from REGN to power ground. The REGN LDO output is used for the internal MOSFETs gate driving voltage and the voltage bias for TS pin resistor divider.
D+ 6 AIO Positive Line of the USB Data Line Pair – D+/D- based USB host/charging port detection for VIN1 input. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and the adjustable high voltage adapter.
D- 7 AIO Negative Line of the USB Data Line Pair – D+/D- based USB host/charging port detection for VIN1 input. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and the adjustable high voltage adapter.
VAC2 8 P VAC2 Input Detection – When a voltage between 3.6V and 24V is applied on VAC2, it represents a valid input being plugged into port #2. Connect to VBUS if the ACFET2 and RBFET2 are not installed.
VAC1 9 P VAC1 Input Detection – When a voltage between 3.6V and 24V is applied on VAC1, it represents a valid input being plugged into port #1. Connect to VBUS if the ACFET1 and RBFET1 are not installed.
ACDRV2 10 P Input FETs Driver Pin 2 – The charge pump output to drive the port #2 input N-channel MOSFET (ACFET2) and the reverse blocking N-channel MOSFET (RBFET2). The charger turns on the back-to-back MOSFETs by increasing the ACDRV2 voltage 5V above the common source connection of the ACFET2 and RBFET2 when the turn-on condition is met. Tie ACDRV2 to GND if no ACFET2 and RBFET2 installed.
ACDRV1 11 P Input FETs Driver Pin 1 – The charge pump output to drive the port #1 input N-channel MOSFET (ACFET1) and the reverse blocking N-channel MOSFET (RBFET1). The charger turns on the back-to-back MOSFETs by increasing the ACDRV1 voltage 5V above the common source connection of the ACFET1 and RBFET1 when the turn-on condition is met. Tie ACDRV1 to GND if no ACFET1 and RBFET1 installed.
QON 12 DI Ship FET Enable or System Power Reset Control Input – When the device is in ship mode or in the shutdown mode, the SDRV turns off the external ship FET to minimize the battery leakage current. A logic low on this pin with tSM_EXIT duration turns on ship FET to force the device to exit the ship mode. A logic low on this pin with tRST duration resets system power by turning off the ship FET for tRST_SFET (also setting the charger in HIZ mode when VBUS is high) and then turning on ship FET (also disabling the charger HIZ mode) to provide full system power reset. During tRST_SFET when the ship FET is off, the charger applies a 30mA discharging current on SYS to discharge system voltage. The pin contains an internal pull-up through a RQON resistor. The typical output voltage is 3.6 V-3.8 V with VBUS and VBAT > 5V.
CE 13 DI Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating.
SCL 14 DI I2C Interface Clock – Connect SCL to the logic rail through a 10 kΩ resistor.
SDA 15 DIO I2C Interface Data – Connect SDA to the logic rail through a 10 kΩ resistor.
TS 16 AI Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin voltage is out of range. Recommend a 103AT-2 10kΩ thermistor.
ILIM_HIZ 17 AI Input Current Limit Setting and HIZ Mode Control Pin – Program ILIM_HIZ voltage by connecting a resistor divider from pull up rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: VILIM_HIZ = 1V + 800mΩ × IINDPM, in which IINDPM is the target input current. The input current limit used by the charger is the lower setting of ILIM_HIZ pin and the IINDPM register. When the pin voltage is below 0.75V, the buck converter enters non-switching mode, similar to HiZ mode using EN_HIZ bit, but with REGN on. When the pin voltage is above 1V, the converter resumes switching. Connect ILIM_HIZ to REGN to set the maximum input current limit.
BATP 18 P Positive Input for Battery Voltage Sensing – Connect to the positive terminal of battery pack. Place 100Ω series resistance between this pin and the battery positive terminal.
BTST2 19 P Output High Side Power MOSFET Gate Driver Power Supply – Connect a 10V or higher rating, 47nF ceramic capacitor between SW2 and BTST2 as the bootstrap capacitor for driving high side switching MOSFET (Q4).
PROG 20 AI Charger POR Default Settings Program – At power up, the charger detects the resistance tied to PROG pin to determine the default switching frequency and the default battery charging profile. The surface mount resistor with ±1% or ±2% tolerance is recommended. Please refer to more details in the section of PROG Pin Configuration.
INT 21 DO Open Drain Interrupt Output. – Connect the INT pin to a logic rail via a 10kΩ resistor. The INT pin sends an active low, 256μs pulse to the host to report the charger device status and faults.
BAT 22-23 P The Battery Charging Power Connection – Connect to the positive terminal of the battery pack. The internal charging current sensing circuit is connected between SYS and BAT. The recommended capacitors at BAT are 2 pieces of 10μF ceramic capacitors.
SDRV 24 P External N-channel Ship FET (SFET) Gate Driver Output – The driver pin of the external ship FET. The ship FET is always turned on when the ship mode is disabled, and it keeps off when the charger is in ship mode or shutdown mode. Connect a 1nF, 50V rated, 0402 package, ceramic capacitor from SDRV to GND when the ship FET is not used.
SYS 25 P The Charger Output Voltage to System – The internal N-channel high side MOSFET (Q4) is connected between SYS and SW2 with drain on SYS and source on SW2. The recommended capacitors at SYS are 5 pieces of 10μF and one piece of 0.1μF ceramic capacitors. Place the 0.1μF ceramic capacitor as close as possible to the charger IC.
SW2 26 P Boost Side Half Bridge Switching Node Inductor connection to mid point of Q3 and Q4 switches.
GND 27 P Ground Return
SW1 28 P Buck Side Half Bridge Switching Node Inductor connection to mid point of Q1 and Q2 switches.
PMID 29 P Q1 MOSFET Drain Connection – An internal N-channel high side MOSFET (Q1) is connected between PMID and SW1 with drain on PMID and source on SW1. The recommended capacitors at PMID are 3 pieces of 10μF and one piece of 0.1μF ceramic capacitors. Place the 0.1μF ceramic capacitor as close as possible to the charger IC.
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