ZHCSLT1B december   2020  – july 2023 BQ25672

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Device Power Up from Battery without Input Source
      4. 8.3.4  Device Power Up from Input Source
        1. 8.3.4.1 Power Up REGN LDO
        2. 8.3.4.2 Poor Source Qualification
        3. 8.3.4.3 ILIM_HIZ Pin
        4. 8.3.4.4 Default VINDPM Setting
        5. 8.3.4.5 Input Source Type Detection
          1. 8.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 8.3.4.5.2 HVDCP Detection Procedure
          3. 8.3.4.5.3 Connector Fault Detection
      5. 8.3.5  Dual-Input Power Mux
        1. 8.3.5.1 VBUS Input Only
        2. 8.3.5.2 One ACFET-RBFET
        3. 8.3.5.3 Two ACFETs-RBFETs
      6. 8.3.6  Buck Converter Operation
        1. 8.3.6.1 Force Input Current Limit Detection
        2. 8.3.6.2 Input Current Optimizer (ICO)
        3. 8.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 8.3.6.4 Pulse Frequency Modulation (PFM)
        5. 8.3.6.5 Device HIZ State
      7. 8.3.7  USB On-The-Go (OTG)
        1. 8.3.7.1 OTG Mode to Power External Devices
      8. 8.3.8  Power Path Management
        1. 8.3.8.1 Narrow Voltage DC Architecture
        2. 8.3.8.2 Dynamic Power Management
      9. 8.3.9  Battery Charging Management
        1. 8.3.9.1 Autonomous Charging Cycle
        2. 8.3.9.2 Battery Charging Profile
        3. 8.3.9.3 Charging Termination
        4. 8.3.9.4 Charging Safety Timer
        5. 8.3.9.5 Thermistor Qualification
          1. 8.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 8.3.10 Integrated 16-Bit ADC for Monitoring
      11. 8.3.11 Status Outputs ( STAT, and INT)
        1. 8.3.11.1 Charging Status Indicator (STAT Pin)
        2. 8.3.11.2 Interrupt to Host ( INT)
      12. 8.3.12 Ship FET Control
        1. 8.3.12.1 Shutdown Mode
        2. 8.3.12.2 Ship Mode
        3. 8.3.12.3 System Power Reset
      13. 8.3.13 Protections
        1. 8.3.13.1 Voltage and Current Monitoring
          1. 8.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 8.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 8.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 8.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 8.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 8.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 8.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 8.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 8.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 8.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 8.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 8.3.14 Serial Interface
        1. 8.3.14.1 Data Validity
        2. 8.3.14.2 START and STOP Conditions
        3. 8.3.14.3 Byte Format
        4. 8.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.14.5 Target Address and Data Direction Bit
        6. 8.3.14.6 Single Write and Read
        7. 8.3.14.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息
8.3.4.5.1 D+/D– Detection Sets Input Current Limit

The device contains a D+/D- based input source detection to set the input current limit. The D+/D- detection has four major steps: Data Contact Detect (DCD), Primary Detection, Secondary Detection and High Voltage DCP (HVDCP) detection.

The D+/D- Primary Detection includes standard USB BC1.2 and non-standard adapters. When an input source is plugged in, the device starts standard USB BC1.2 detection first. The USB BC1.2 is capable of identifying Standard Downstream Port (SDP), Charging Downstream Port (CDP) and Dedicated Charging Port (DCP). The non-standard detection is used to distinguish vendor specific adapters based on the unique dividers they apply to the D+/D- pins. The secondary detection is used to distinguish two types of charging ports, CDP and DCP.

A CDP usually requires the attached device to send back an enumeration within 2.5 seconds of CDP plug-in. Otherwise, the port will power cycle back to SDP even the D+/D- detection indicates CDP. This enumeration must be handled externally to the charger.

GUID-20201027-CA0I-6PBX-97WP-NPHQL4XV6LHT-low.gif Figure 8-1 D+/D– Detection Flow
Table 8-3 Non-Standard Adapter Detection
NON-STANDARD ADAPTER D+ THRESHOLD D– THRESHOLD INPUT CURRENT LIMIT
Divider 1 VD+ within V2P8_VTH VD– within V2P0_VTH 2.1 A
Divider 2 VD+ within V1P2_VTH VD+ within V1P2_VTH 2A
Divider 3 VD+ within V2P0_VTH VD– within V2P8_VTH 1 A
Divider 4 VD+ within V2P8_VTH VD– within V2P8_VTH 2.4 A

When a Dedicated Charging Port (DCP) is detected, the charger initiates two high voltage adapter (HVDCP) handshakes to enable the corresponding adapter to output a higher voltage for fast charging. The HVDCP detection can be enabled by setting EN_HVDCP=1 and then setting either EN_9V=1 to increase the input voltage to 9V or EN_12V=1 to increase the input voltage to 12V. When EN_12V and EN_9V are both set to 1, the charger starts 12V first.

After the input source type detection is done, the DPDM_STAT bit is set to 0, an INT pulse and DPDM_DONE_FLAG are asserted if DPDM_DONE_MASK = 0. In addition, REG06_Input_Current_Limit and VBUS_STAT are updated as shown in Table 8-4.

Table 8-4 Input Current Limit Setting from D+/D– Detection
D+/D– DETECTION INPUT CURRENT LIMIT (IINDPM) VBUS_STAT_3:0
USB SDP 500 mA 0001
USB CDP 1.5 A 0010
USB DCP 3.25 A 0011
Adjustable High Voltage DCP (HVDCP) 1.5A 0100
Unknown Adapter 3 A 0101
Non-Standard Adapter, Divider 1 2.1 A 0110
Non-Standard Adapter, Divider 2 2 A 0110
Non-Standard Adapter, Divider 3 1 A 0110
Non-Standard Adapter, Divider 4 2.4 A 0110
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