The device supports the OTG operation to deliver power from the battery to other external devices through the USB ports. The OTG voltage regulation is set in VOTG[10:0] register bits. The OTG current regulation is set in IOTG[6:0] register bits. To enable the OTG operation, the following conditions have to be valid:

• The battery voltage is higher than V_{BAT_OTG} rising threshold, and not trigger the VBAT_OVP protection.
• The VBUS is below V_{VBUS_UVLO}.
• The voltage at TS pin is within the range configured by BHOT and BCOLD register bits

If the ACFET1-RBFET1 and the ACFET2-RBFET2 are not detected (ACRB1_STAT = 0 and ACRB2_STAT = 0) at POR, the converter starts up with typical 5ms delay after the EN_OTG bit is set to 1, then the VBUS voltage ramps up to the VOTG register setting.

The following cases explain the charger OTG mode behaviors when the ACFET1-RBFET1 or/and ACFET2-RBFET2 are present.

• If only ACRB1_STAT=1 OR only ACRB2_STAT = 1, which means only one input ACFET-RBFET is present, the converter stays in the non-switching mode after the EN_OTG bit is set, until the host writes EN_ACDRV1 = 1 (when only ACRB1_STAT = 1) or EN_ACDRV2 = 1 (when only ACRB2_STAT = 1). The converter starts up with 5ms delay after the EN_ACDRV1 or EN_ACDRV2 bit is set to 1, then VBUS voltage ramps up to the VOTG register setting.
• If both ACRB1_STAT = 1 AND ACRB2_STAT = 1, which means two input ACFET-RBFET are present, the converter stays in the non-switching mode after the EN_OTG bit is set, until the host writes either EN_ACDRV1 = 1 or EN_ACDRV2 = 1. The converter starts up with 5ms delay after the EN_ACDRV1 or EN_ACDRV2 bit is set to 1, then VBUS voltage ramps up to the VOTG register setting.
• Regardless of ACRB1_STAT and ACRB2_STAT, if DIS_ACDRV = 1, the ACDRV is disabled. The converter starts up with 5ms delay after the EN_OTG bit is set to 1, then VBUS voltage ramps up to the VOTG register setting. The operation is the same as that when ACFET1-RBFET1 and ACFET2-RBFET2 are not detected.
• For swapping the OTG output from port 1 to port 2, assuming EN_ACDRV2 is already 0, the host has to set EN_ACDRV1 = 0 to turn off ACFET1_RBFET1 first, which causes the converter to stop switching and VBUS to drop below V_{BUS_PRESENT}. The host sets EN_ACDRV2 = 1, the converter starts switching again and ACDRV2 turns on ACFET2-RBFET2, which allows VBUS to ramp up. The similar procedure can be applied to the case of swapping the OTG output from port 2 to port 1.

In OTG mode, the converter PFM operation can be disabled by setting PFM_OTG_DIS = 1 and the OOA can be disabled by setting DIS_OTG_OOA = 1.

The simplified application diagram for the OTG mode operation is shown as the figure above, in which the power flow is illustrated by the blue arrows.

The charger is also monitoring the battery discharging current in OTG mode. When IBAT rises higher than the IBAT_REG[1:0] register setting, the charger reduces the OTG output current and prioritizes the system load current if there is any. The IBAT_REG_STAT bit is set to 1 and an INT pulse is asserted and the IBAT_REG_FLAG is set to 1, if IBAT_REG_MASK = 0. If the OTG output current is decreased to zero and the system load pulls even more current, the charger can no longer limit the battery discharging current.