The switching nodes rising and falling times should be minimized for minimum switching loss. Proper layout of the components to minimize the high frequency current path loops (shown in the figure below) is important to prevent the electrical and magnetic field radiation and the high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

1. Place the SYS output capacitors as close to SYS and GND as possible. Place a 0.1 µF small size (such as 0402 or 0201) capacitor closer than the other 10 µF capacitors. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
2. Place the PMID input capacitors as close to PMID and GND as possible. Place a 0.1 µF small size (such as 0402 or 0201) capacitor closer than the other 10 µF capacitors. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
3. Place the VBUS input capacitors as close to VBUS and GND as possible. Place a 0.1 µF small size (such as 0402 or 0201) capacitor closer than the other 10 µF capacitors. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
4. The connection from SYS/PMID/VBUS to the 0.1 µF has to be routed on the top layer of the PCB, the returning back to GND also has to be in the top layer. Keep the whole routing loop as small as possible.
5. Place the inductor input terminal to SW1 and the inductor output terminal to SW2 as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the inductor current. Minimize parasitic capacitance from this area to any other trace or plane.
6. Place the BAT capacitors close to BAT and GND, place the VBUS capacitors close to VBUS and GND.
7. The REGN decoupling capacitor and the bootstrap capacitors should be placed next to the IC and make trace connection as short as possible.
8. Ensure that there are sufficient thermal vias directly under the power MOSFETs, connecting to copper on other layers.
9. Via size and number should be enough for a given current path.
10. Route BATP away from switching nodes such as SW1 and SW2.

    Refer to the EVM design and more information in the BQ25672EVM (BMS027) Evaluation Module User's Guide for the recommended component placement with trace and via locations.

Figure 11-1 Buck-Boost Converter High Frequency Current Path