8.3.2.1 CHRG_OK Indicator

CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the following conditions are valid:

• VBUS is above V_{VBUS_CONVEN}
• VBUS is below V_ACOV
• No MOSFET/inductor fault

8.3.2.2 Input Voltage and Current Limit Setup

When CHRG_OK goes LOW, the charger sets default input current limit in REG0x3F() to 3.30A. The actual input current limit is the lower setting of REG0x3F() and ILIM_HIZ pin.

Charger initiates a VBUS voltage measurement without any load (VBUS at no load condition). The default VINDPM threshold is VBUS@noLoad-1.28 V.

After input current and voltage limits are set, the charger device is ready to power up. The host can always update input current and voltage limit based on input source type.

8.3.2.3 Battery Cell Configuration

CELL_BATPRESZ pin is biased with resistors from REGN to CELL_BATPRESZ to GND. After VDDA LDO is activated, the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. Refer to Electrical Characteristics for CELL setting thresholds.

8.3.2.4 Device Hi-Z State

The charger enters Hi-Z mode when ILIM_HIZ pin voltage is below 0.4 V or REG0x32[15] is set to 1. During Hi-Z mode, the input source is present, and the charger is in the low quiescent current mode with REGN LDO enabled.

Table 2. MOSFET Operation

8.3.3.1 Inductor Setting through IADPT Pin

The charger reads the inductor value through the IADPT pin.

8.3.3.2 Continuous Conduction Mode (CCM)

With sufficient charge current, the inductor current does not cross 0 A, which is defined as CCM. The controller starts a new cycle with ramp coming up from 200 mV. As long as error amplifier output voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error amplifier output voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current.

During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on when the HSFET is off, keeps the power dissipation low and allows safe charging at high currents.

8.3.3.3 Pulse Frequency Modulation (PFM)

In order to improve converter light-load efficiency, the bq25708 switches to PFM control at light load condition. The effective switching frequency will decrease accordingly when system load decreases. The minimum frequency can be limit to 25kHz (ChargeOption0() bit[10]=1).

8.3.4.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)

As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current during forward charging, and the charge/discharge current (IBAT). IADPT voltage is 20× or 40× the differential voltage across ACP and ACN. IBAT voltage is 8x/16× (during charging), or 8×/16× (during discharging) of the differential across SRP and SRN. After input voltage or battery voltage is above UVLO, IADPT output becomes valid. To lower the voltage on current monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be achieved.

• V_(IADPT) = 20 or 40 × (V_(ACP) – V_(ACN)) during forward mode.
• V_(IBAT) = 8 or 16 × (V_(SRP) – V_(SRN)) during forward charging mode.
• V_(IBAT) = 8 or 16 × (V_(SRN) – V_(SRP)) during forward supplement mode.

A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The CSA output voltage is clamped at 3.3 V.

8.3.4.2 High-Accuracy Power Sense Amplifier (PSYS)

The charger monitors total system power. During forward mode, the input adapter powers system. The ratio of PSYS current and total power K_PSYS can be programmed in REG0x30[9] with default 1 μA/W. The input and charge sense resistors (RAC and RSR) are programmed in REG0x30[11:10]. PSYS voltage can be calculated with Equation 1 where IIN>0 when adapter is in forward charging, and IBAT>0 when the battery is in discharge when the battery is in discharge.

Equation 1.

For proper PSYS functionality, RAC and RSR values are limited to 10mΩ and 20mΩ.

8.3.7.1 PROCHOT During Low Power Mode

During low power mode (REG0x12[15]=1), the charger offers a low quiescent current (~150 uA) Low power PROCHOT function uses the independent comparator to monitor battery discharge current and system voltage, and assert PROCHOT to CPU.

Below lists the register setting to enable PROCHOT during low power mode.

• REG0x12[15]=1
• REG0x34[5:0]=000000
• REG0x30[6:4]=100
• Independent comparator threshold is always 1.2V
• When REG0x30[14]=1, charger monitors discharge current. Connect CMPIN to voltage proportional to IBAT pin. PROCHOT triggers from HIGH to LOW when CMPIN voltage falls below 1.2V.
• When REG0x30[13]=1, charger monitors system voltage. Connect CMPIN to voltage proportional to system. PROCHOT triggers from HIGH to LOW when CMPIN voltage rises above 1.2V.

Figure 10. PROCHOT Low Power Mode Implementation

8.3.7.2 PROCHOT Status

REG0x21[6:0] reports which event in the profile triggers PROCHOT by setting the corresponding bit to 1. The status bit can be reset back to 0 after it is read by host, and current PROCHOT event is no longer active.

Assume there are two PROCHOT events, event A and event B. Event A triggers PROCHOT first, but event B is also active. Both status bits will be HIGH. At the end of the 10ms PROCHOT pulse, if PROCHOT is still active (either by A or B), the PROCHOT pulse is extended.

8.3.8.1 Watchdog Timer

The charger includes watchdog timer to terminate charging if the charger does not receive a write MaxChargeVoltage() or write ChargeCurrent() command within 175 s (adjustable via REG0x12[14:13]). When watchdog timeout occurs, all register values are kept unchanged except ChargeCurrent() resets to zero. Battery charging is suspended. Write MaxChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. Writing REG0x12[14:13] = 00 to disable watchdog timer also resumes charging.

8.3.8.2 Input Overvoltage Protection (ACOV)

The charger has fixed ACOV voltage. When VBUS pin voltage is higher than ACOV, it is considered as adapter over voltage. CHRG_OK will be pulled low, and converter will be disabled. As system falls below battery voltage, BATFET will be turned on. When VBUS pin voltage falls below ACOV, it is considered as adapter voltage returns back to normal voltage. CHRG_OK will be pulled high by external pull up resistor. The converter will resume if enable conditions are valid.

8.3.8.3 Input Overcurrent Protection (ACOC)

If the input current exceeds the 1.25× or 2× (REG0x31[2]) of I_{LIM2_VTH} (REG0x33[15:11]) set point, converter stops switching. After 300 ms, converter will start switching again.

8.3.8.4 System Overvoltage Protection (SYSOVP)

When the converter starts up, the bq25708 reads CELL pin configuration and sets MaxChargeVoltage() and SYSOVP threshold (1s – 5 V, 2s – 12 V, 3s/4s – 19.5 V). Before REGx15() is written by host, the battery configuration will change with CELL pin voltage. When SYSOVP happens, the device latches off the converter. REG20[4] is set as 1. The user can clear the latch-off by either writing 0 to SYSOVP bit or removing and plugging in adapter again. After the latch-off is cleared, converter starts again.

8.3.8.5 Battery Overvoltage Protection (BATOVP)

Battery over-voltage may happen when battery is removed during charging or the user plugs in a wrong battery. The BATOVP threshold is 104% (1 s) or 102% (2 s to 4 s) of regulation voltage set in REG0x15().

8.3.8.6 Battery Short

If BAT voltage falls below SYSMIN during charging, the maximum current is limited to 384 mA.

8.3.8.7 Thermal Shutdown (TSHUT)

The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shut down, the LDO current limit is reduced to 16 mA and REGN LDO stays off. When the temperature falls below 135°C, charge can be resumed with soft start.

8.4.1.1 System Voltage Regulation with Narrow VDC Architecture

The bq25708 employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by MinSystemVoltage(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode).

As the battery voltage rises above the minimum system voltage, BATFET is fully on when charging or in supplement mode and the voltage difference between the system and battery is the VDS of BATFET. System voltage is regulated 160 mV above battery voltage when BATFET is off (no charging or no supplement current).

See System Voltage Regulation for details on system voltage regulation and register programming.

8.4.1.2 Battery Charging

The bq25708 charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. Based on CELL_BATPREZ pin setting, the charger sets default battery voltage 4.2V/cell to ChargeVoltage(), or REG0x15(). According to battery capacity, the host programs appropriate charge current to ChargeCurrent(), or REG0x14(). When battery is full or battery is not in good condition to charge, host terminates charge by setting REG0x12[0] to 1, or setting ChargeCurrent() to zero.

See Feature Description for details on register programming.

8.5.1.1 SMBus Write-Word and Read-Word Protocols

8.5.1.2 Timing Diagrams

A = Start condition	H = LSB of data clocked into slave
B = MSB of address clocked into slave	I = Slave pulls SMBDATA line low
C = LSB of address clocked into slave	J = Acknowledge clocked into master
D = R/W bit clocked into slave	K = Acknowledge clock pulse
E = Slave pulls SMBDATA line low	L = Stop condition, data executed by slave
F = ACKNOWLEDGE bit clocked into master	M = New start condition
G = MSB of data clocked into slave

Figure 11. SMBus Write Timing

A = Start condition	G = MSB of data clocked into master
B = MSB of address clocked into slave	H = LSB of data clocked into master
C = LSB of address clocked into slave	I = Acknowledge clock pulse
D = R/W bit clocked into slave	J = Stop condition
E = Slave pulls SMBDATA line low	K = New start condition
F = ACKNOWLEDGE bit clocked into master

Figure 12. SMBus Read Timing

8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]

8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]

8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]

8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]

8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]

8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]

8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]

8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]

8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]

Table 25. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions

Table 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions

8.6.3.1 Battery Pre-Charge Current Clamp

During pre-charge, BATFET works in linear mode or LDO mode (default REG0x12[2] = 1). For 2-4 cell battery, the system is regulated at minimum system voltage in REG0x3E() and the pre-charge current is clamped at 384 mA. For 1 cell battery, the pre-charge to fast charge threshold is 3V, and the pre-charge current is clamped at 384mA. However, the BATFET stays in LDO mode operation till battery voltage is above minimum system voltage (~3.6V). During battery voltage from 3V to 3.6V, the fast charge current is clamped at 2A.

Table 27. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions

Table 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions

Table 29. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions

Table 30. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions

8.6.5.1 System Voltage Regulation

The device employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG0x3E(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage with BATFET.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on when charging or in supplement mode and the voltage difference between the system and battery is the VDS of BATFET. System voltage is regulated 160mV above battery voltage when BATFET is off (no charging or no supplement current).

When BATFET is removed, the system node VSYS is shorted to SRP. Before the converter starts operation, LDO mode needs to be disabled. The following sequence is required to configure charger without BATFET.

1. Before adapter plugs in, put the charger into HIZ mode. (either pull pin 6 ILIM_HIZ to ground, or set REG0x32[15] to 1)
2. Set 0x12[2] to 0 to disable LDO mode.
3. Set 0x30[0] to 0 to disable auto-wakeup mode.
4. Check if battery voltage is properly programmed (REG0x15)
5. Set pre-charge/charge current (REG0x14)
6. Put the device out of HIZ mode. (Release ILIM_HIZ from ground and set REG0x32[15]=0).

In order to prevent any accidental SW mistakes, the host sets low input current limit (a few hundred milliamps) when device is out of HIZ.

8.6.6.1 Input Current Registers

To set the maximum input current limit, write a 16-bit IIN_HOST register command (REG0x3F()) using the data format listed in Figure 25. When using a 10-mΩ sense resistor, the charger provides an input-current limit range of 50 mA to 6400 mA, with 50-mA resolution. The default current limit is 3.3 A. Due to the USB current setting requirement, the register setting specifies the maximum current instead of the typical current. Upon adapter removal, the input current limit is reset to the default value of 3.3 A. The register setting is clamped at 50mA. With code 00h and 01h, the input current limit settings are both 50mA.

The ACP and ACN pins are used to sense R_AC with the default value of 10 mΩ. For a 20 mΩ sense resistor, a larger sense voltage is given and a higher regulation accuracy, but at the expense of higher conduction loss.

Instead of using the internal DPM loop, the user can build up an external input current regulation loop and have the feedback signal on the ILIM_HIZ pin.

Equation 2.

In order to disable ILIM_HIZ pin, the host can write to 0x31[7] to disable ILIM_HIZ pin, or pull ILIM_HIZ pin above 4 V.

Table 37. ADCVBUS/PSYS Register Field Descriptions

Table 38. ADCIBAT Register Field Descriptions

Table 39. ADCIINCMPIN Register Field Descriptions

Table 40. ADCVSYSVBAT Register Field Descriptions

8.6.11.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]

8.6.11.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]