米6体育平台手机版

SLUSCU2 November 2017

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RSN|32
- MPQF194B

散热焊盘机械数据 (封装 | 引脚)

RSN|32
- QFND189E

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Voltage	SRN, SRP, ACN, ACP, VBUS, VSYS, BATDRV	–0.3	30	V
	SW1, SW2	–2.0	30
	BTST1, BTST2, HIDRV1, HIDRV2	–0.3	36
	LODRV1, LODRV2 (25 ns)	–4.0	7
	HIDRV1, HIDRV2 (25 ns)	–4.0	36
	SW1, SW2 (25 ns)	–4.0	30
	SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ, LODRV1, LODRV2, VDDA, COMP1, COMP2, CMPIN, CMPOUT	–0.3	7
	PROCHOT	–0.3	5.5
	IADPT, IBAT, PSYS	–0.3	3.6
Differential voltage	BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2	–0.3	7	V
Differential voltage	SRP-SRN, ACP-ACN	–0.5	0.5	V
Junction temperature range, T_J		–40	155	°C
Storage temperature, T_stg		–40	155	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Voltage	ACN, ACP, VBUS	0	24	V
	SRN, SRP, VSYS, BATDRV	0	19.2
	SW1, SW2	–2	24
	BTST1, BTST2, HIDRV1, HIDRV2	0	30
	SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ, LODRV1, LODRV2, VDDA, COMP1, COMP2, CMPIN, CMPOUT	0	6.5
	PROCHOT	0	5.3
	IADPT, IBAT, PSYS	0	3.3
Differential voltage	BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2	0	6.5	V
Differential voltage	SRP-SRN, ACP-ACN	–0.35	0.35	V
Junction temperature, T_J		–40	125	°C
Operating free-air temperature, T_A		–40	85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq25708	UNIT
		RSN (WQFN)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	37.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	26.1	°C/W
R_θJB	Junction-to-board thermal resistance	7.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	7.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{INPUT_OP}	Input voltage operating range		3.5		26	V
REGULATION ACCURACY
MAX SYSTEM VOLTAGE REGULATION
V_{SYSMAX_RNG}	System voltage regulation, measured on V_SYS		1.024		19.2	V
V_{SYSMAX_ACC}	System voltage regulation accuracy (charge disable)	REG0x15() = 0x41A0H (16.800 V)		V_SRN + 160 mV		V
		REG0x15() = 0x41A0H (16.800 V)	–2%		2%
		REG0x15() = 0x3130H (12.592 V)		V_SRN + 160 mV		V
		REG0x15() = 0x3130H (12.592 V)	–2%		2%
		REG0x15() = 0x20D0H (8.400 V)		V_SRN + 160 mV		V
		REG0x15() = 0x20D0H (8.400 V)	–3%		3%
		REG0x15() = 0x1060H (4.192 V)		V_SRN + 160 mV		V
		REG0x15() = 0x1060H (4.192 V)	–3%		3%
MINIMUM SYSTEM VOLTAGE REGULATION
V_{SYSMIN_RNG}	System voltage regulation, measured on V_SYS		1.024		19.2	V
V_{SYSMIN_REG_ACC}	Minimum system voltage regulation accuracy (charge enable, VBAT below REG0x3E() setting)	REG0x3E() = 0x3000H		12.288		V
		REG0x3E() = 0x3000H	–2%		2%
		REG0x3E() = 0x2400H		9.216		V
		REG0x3E() = 0x2400H	–2%		2%
		REG0x3E() = 0x1800H		6.144		V
		REG0x3E() = 0x1800H	–3%		3%
		REG0x3E() = 0x0E00H		3.584		V
		REG0x3E() = 0x0E00H	–3%		4%
CHARGE VOLTAGE REGULATION
V_{BAT_RNG}	Battery voltage regulation		1.024		19.2	V
V_{BAT_REG_ACC}	Battery voltage regulation accuracy (charge enable) (0°C to 85°C)	REG0x15() = 0x41A0H		16.8		V
		REG0x15() = 0x41A0H	–0.5%		0.5%
		REG0x15() = 0x3130H		12.592		V
		REG0x15() = 0x3130H	–0.5%		0.5%
		REG0x15() = 0x20D0H		8.4		V
		REG0x15() = 0x20D0H	–0.6%		0.6%
		REG0x15() = 0x1060H		4.192		V
		REG0x15() = 0x1060H	–1.1%		1.2%
CHARGE CURRENT REGULATION IN FAST CHARGE
V_{IREG_CHG_RNG}	Charge current regulation differential voltage range	VIREG_CHG = VSRP – VSRN	0		81.28	mV
I_{CHRG_REG_ACC}	Charge current regulation accuracy 10-mΩ current sensing resistor, VBAT above 0x3E() setting (0°C to 85°C)	REG0x14() = 0x1000H		4096		mA
		REG0x14() = 0x1000H	–3%		2%
		REG0x14() = 0x0800H		2048		mA
		REG0x14() = 0x0800H	–4%		3%
		REG0x14() = 0x0400H		1024		mA
		REG0x14() = 0x0400H	–5%		5%
		REG0x14() = 0x0200H		512		mA
		REG0x14() = 0x0200H	–12%		12%
CHARGE CURRENT REGULATION IN LDO MODE
I_CLAMP	Pre-charge current clamp	CELL 2s-4s		384		mA
		CELL 1 s, V_SRN < 3 V		384		mA
		CELL 1 s, 3 V < V_SRN < V_{SYS_MIN}		2		A
I_{PRECHRG_REG_ACC}	Pre-charge current regulation accuracy with 10-mΩ SRP/SRN series resistor, VBAT below REG0x3E() setting (0°C to 85°C)	REG0x14() = 0x0180H		384		mA
		2S-4S	–15%		15%
		1S	–25%		25%
		REG0x14() = 0x0100H		256		mA
		2S-4S	–20%		20%
		1S	–35%		35%
		REG0x14() = 0x00C0H		192		mA
		2S-4S	–25%		25%
		1S	–50%		50%
		REG0x14() = 0x0080H		128		mA
		2S-4S	–30%		30%
I_{LEAK_SRP_SRN}	SRP, SRN leakage current mismatch (0°C to 85°C)		–12		–10	µA
INPUT CURRENT REGULATION
V_{IREG_DPM_RNG}	Input current regulation differential voltage range	V_{IREG_DPM} = V_ACP – V_ACN	0.5		64	mV
I_{DPM_REG_ACC}	Input current regulation accuracy with 10-mΩ ACP/ACN series resistor (–40°C to 105°C)	REG0x3F() = 0x4FFFH	3820		4000	mA
		REG0x3F() = 0x3BFFH	2830		3000	mA
		REG0x3F() = 0x1DFFH	1350		1500	mA
		REG0x3F() = 0x09FFH	340		500	mA
I_{LEAK_ACP_ACN}	ACP, ACN leakage current mismatch		–16		10	µA
V_{IREG_DPM_RNG_ILIM}	Voltage Range for input current regulation		1		4	V
I_{DPM_REG_ACC_ILIM}	Input Current Regulation Accuracy on ILIM_HIZ pin V_{ILIM_HIZ} = 1 V + 40 × IDPM × R_AC, with 10-mΩ ACP/ACN series resistor	V_{ILIM_HIZ} = 2.6 V	3800	4000	4200	mA
		V_{ILIM_HIZ} = 2.2 V	2800	3000	3200	mA
		V_{ILIM_HIZ} = 1.6 V	1300	1500	1700	mA
		V_{ILIM_HIZ} = 1.2 V	300	500	700	mA
I_{LEAK_ILIM}	I_{LIM_HIZ} pin leakage		–1		1	µA
INPUT VOLTAGE REGULATION
V_{IREG_DPM_RNG}	Input voltage regulation range	Voltage on VBUS	3.2		19.52	V
V_{DPM_REG_ACC}	Input voltage regulation accuracy	REG0x3D()=0x3C80H		18688		mV
			–2%		2%
		REG0x3D()=0x1E00H		10880		mV
			–2.5%		2.5%
		REG0x3D()=0x0500H		4480		mV
			–3%		5%
REFERENCE AND BUFFER
REGN REGULATOR
V_{REGN_REG}	REGN regulator voltage (0 mA–60 mA)	V_VBUS = 10 V	5.7	6	6.3	V
V_DROPOUT	REGN voltage in drop out mode	V_VBUS = 5 V, I_LOAD = 20 mA	3.8	4.3	4.6	V
I_{REGN_LIM_Charging}	REGN current limit when converter is enabled	V_VBUS = 10 V, force V_REGN = 4 V	50	65		mA
C_REGN	REGN output capacitor required for stability	I_LOAD = 100 µA to 50 mA	2.2			µF
C_VDDA	REGN output capacitor required for stability	I_LOAD= 100 µA to 50 mA	1			µF
QUIESCENT CURRENT
I_{BAT_BATFET_ON}	System powered by battery. BATFET on. I_SRN + I_SRP + I_SW2+ I_BTST2 + I_SW1 + I_BTST1+ _ACP + I_ACN + I_VBUS + I_VSYS	VBAT = 18 V, REG0x12[15] = 1, in low power mode		22	45	µA
		VBAT = 18 V, REG0x12[15] = 1, in low power mode, REG0x30[14:13] = 01, REGN off		105	175	µA
		VBAT=18 V, REG0x12[15] = 1, in low power mode, REG0x30[14:13]= 10, REGN off		60	90	µA
		VBAT = 18 V, REG0x12[15] = 0, REG0x30[12] = 0, REGN on, EN_PSYS		860	1150	µA
		VBAT = 18 V, REG0x12[15] = 0, REG0x30[12] = 1, REGN on		960	1250	µA
I_{AC_SW_LIGHT_buck}	Input current during PFM in buck mode, no load, I_VBUS + I_ACP + I_ACN + I_VSYS + I_SRP + I_SRN + I_SW1 + I_BTST + I_SW2 + I_BTST2	VIN = 20 V, VBAT = 12.6 V, 3 s, REG0x12[10] = 0; MOSFET Qg = 4 nC		2.2		mA
I_{AC_SW_LIGHT_boost}	Input current during PFM in boost mode, no load, I_VBUS + I_ACP + I_ACN + I_VSYS + I_SRP + I_SRN + I_SW1 + I_BTST2 + I_SW2 + I_BTST2	VIN = 5 V, VBAT = 8.4 V, 2 s, REG0x12[10] = 0; MOSFET Qg = 4 nC		2.7		mA
I_{AC_SW_LIGHT_buckboost}	Input current during PFM in buck boost mode, no load, I_VBUS + I_ACP + I_ACN + I_VSYS + I_SRP + I_SRN + I_SW1 + I_BTST1 + I_SW2 + I_BTST2	VIN = 12 V, VBAT = 12 V, REG0x12[10] = 0; MOSFET Qg = 4 nC		2.4		mA
V_{ACP/N_OP}	Input common mode range	Voltage on ACP/ACN	3.8		26	V
V_{IADPT_CLAMP}	I_ADPT output clamp voltage		3.1	3.2	3.3	V
I_IADPT	I_ADPT output current				1	mA
A_IADPT	Input current sensing gain	V_(IADPT) / V_(ACP-ACN), REG0x12[4] = 0		20		V/V
A_IADPT	Input current sensing gain	V_(IADPT) / V_(ACP-ACN), REG0x12[4] = 1		40		V/V
V_{IADPT_ACC}	Input current monitor accuracy	V_(ACP-ACN) = 40.96 mV	–2%		2%
		V_(ACP-ACN) = 20.48 mV	–3%		3%
		V_(ACP-ACN) =10.24 mV	–6%		6%
		V_(ACP-ACN) = 5.12 mV	–10%		10%
C_{IADPT_MAX}	Maximum output load capacitance				100	pF
V_{SRP/N_OP}	Battery common mode range	Voltage on SRP/SRN	2.5		18	V
V_{IBAT_CLAMP}	IBAT output clamp voltage		3.1	3.2	3.3	V
I_IBAT	IBAT output current				1	mA
A_IBAT	Charge and discharge current sensing gain on IBAT pin	V_(IBAT)/ V_(SRN-SRP), REG0x12[3] = 0,		8		V/V
A_IBAT	Charge and discharge current sensing gain on IBAT pin	V_(IBAT)/ V_(SRN-SRP), REG0x12[3] = 1,		16		V/V
I_{IBAT_CHG_ACC}	Charge and discharge current monitor accuracy on IBAT pin	V_(SRN-SRP) = 40.96 mV	–2%		2%
		V_(SRN-SRP) = 20.48 mV	–3%		4%
		V_(SRN-SRP) =10.24 mV	–6%		6%
		V_(SRN-SRP) = 5.12 mV	–12%		12%
C_{IBAT_MAX}	Maximum output load capacitance				100	pF
SYSTEM POWER SENSE AMPLIFIER
V_PSYS	PSYS output voltage range		0		3.3	V
I_PSYS	PSYS output current		0		160	µA
A_PSYS	PSYS system gain	V_(PSYS) / (P_(IN)+ P_(BAT)), REG0x30[9] = 1		1		µA/W
V_{PSYS_ACC}	PSYS gain accuracy (REG0x3B[9] = 1), T_A = 25°C	Adapter only with system power = 19.5 V / 45 W	–5%		5%
V_{PSYS_ACC}	PSYS gain accuracy (REG0x3B[9] = 1), T_A = 25°C	Battery only with system power 11 V / 44 W (25°C)	–5%		5%
V_{PSYS_CLAMP}	PSYS clamp voltage		3		3.3	V
COMPARATOR
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR
V_{VBUS_UVLOZ}	VBUS undervoltage rising threshold	VBUS rising	2.34	2.55	2.77	V
V_{VBUS_UVLO}	VBUS undervoltage falling threshold	VBUS falling	2.2	2.4	2.6	V
V_{VBUS_UVLO_HYST}	VBUS undervoltage hysteresis			150		mV
V_{VBUS_CONVEN}	VBUS converter enable rising threshold	VBUS rising	3.2	3.5	3.9	V
V_{VBUS_CONVENZ}	VBUS converter enable falling threshold	VBUS falling	2.9	3.2	3.5	V
V_{VBUS_CONVEN_HYST}	VBUS converter enable hysteresis			400		mV
BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR
V_{VBAT_UVLOZ}	VBAT undervoltage rising threshold	VSRN rising	2.35	2.55	2.75	V
V_{VBAT_UVLO}	VBAT undervoltage falling threshold	VSRN falling	2.2	2.4	2.6	V
V_{VBAT_UVLO_HYST}	VBAT undervoltage hysteresis			150		mV
BATTERY LOWV COMPARATOR (Pre-charge to Fast Charge Thresold for 1S)
V_{BATLV_FALL}	BATLOWV falling threshold	1 s		2.80		V
V_{BATLV_RISE}	BATLOWV rising threshold			3.00		V
V_{BATLV_RHYST}	BATLOWV hysteresis			200		mV
INPUT OVER-VOLTAGE COMPARATOR (ACOVP)
V_{ACOV_RISE}	VBUS overvoltage rising threshold	VBUS rising	25	26	27	V
V_{ACOV_FALL}	VBUS overvoltage falling threshold	VBUS falling	24	24.5	25	V
V_{ACOV_HYST}	VBUS overvoltage hysteresis			1.5		V
t_{ACOV_RISE_DEG}	VBUS overvoltage rising deglitch	VBUS rising to stop converter		100		µs
t_{ACOV_FALL_DEG}	VBUS overvoltage falling deglitch	VBUS falling to start converter		1		ms
INPUT OVER CURRENT COMPARATOR (ACOC)
V_ACOC	ACP to ACN rising threshold, w.r.t. ILIM2 in REG0x33[15:11]	Voltage across input sense resistor rising, Reg0x31[2] = 1	195%	210%	225%
V_{ACOC_FLOOR}	Measure between ACP and ACN	Set IDPM to minimum	44	50	56	mV
V_{ACOC_CEILING}	Measure between ACP and ACN	Set IDPM to maximum	172	180	188	mV
t_{ACOC_DEG_RISE}	Rising deglitch time	Deglitch time to trigger ACOC		250		µs
t_{ACOC_RELAX}	Relax time	Relax time before converter starts again		250		ms
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)
V_{SYSOVP_RISE}	System overvoltage rising threshold to turn off converter	1 s	4.85	5	5.1	V
		2 s	11.7	12	12.2	V
		3s	18	18.5	19	V
V_{SYSOVP_FALL}	System overvoltage falling threshold	1 s		4.8		V
		2 s		11.5		V
		3s		18		V
I_SYSOVP	Discharge current when SYSOVP stop switching was triggered	on SYS		20		mA
BAT OVER-VOLTAGE COMPARATOR (BATOVP)
V_{BATOVP_RISE}	Overvoltage rising threshold as percentage of V_{BAT_REG}in REG0x15()	1 s, 4.2 V	102.5%	104%	105.7%
V_{BATOVP_RISE}		2 s - 4 s	102.5%	104%	105%
V_{BATOVP_FALL}	Overvoltage falling threshold as percentage of VBAT_REG in REG0x15()	1 s	100%	102%	104%
V_{BATOVP_FALL}		2 s - 4 s	100%	102%	103%
V_{BATOVP_HYST}	Overvoltage hysteresis as percentage of V_{BAT_REG} in REG0x15()	1 s		2%
V_{BATOVP_HYST}		2 s - 4 s		2%
I_BATOVP	Discharge current during BATOVP	on SRP and SRN		20		mA
t_{BATOVP_RISE}	Overvoltage rising deglitch to turn off BATDRV to disable charge			20		ms
CONVERTER OVER-CURRENT COMPARATOR (Q2)
VOCP_limit_Q2	Converter Over-Current Limit	Reg0x31[5]=1		150		mV
VOCP_limit_Q2	Converter Over-Current Limit	Reg0x31[5]=0		210		mV
VOCP_limit_SYSSHORT_Q2	System Short or SRN<2.5 V	Reg0x31[5]=1		45		mV
VOCP_limit_SYSSHORT_Q2	System Short or SRN<2.5 V	Reg0x31[5]=0		60		mV
CONVERTER OVER-CURRENT COMPARATOR (ACX)
VOCP_limit_ACX	Converter Over-Current Limit	Reg0x31[4]=1		150		mV
VOCP_limit_ACX	Converter Over-Current Limit	Reg0x31[4]=0		280		mV
VOCP_limit_SYSSHORT_ ACX	System Short or SRN<2.5 V	Reg0x31[4]=1		90		mV
VOCP_limit_SYSSHORT_ ACX	System Short or SRN<2.5 V	Reg0x31[4]=0		150		mV
THERMAL SHUTDOWN COMPARATOR
T_{SHUT_RISE}	Thermal shutdown rising temperature	Temperature increasing		155		°C
T_{SHUTF_FALL}	Thermal shutdown falling temperature	Temperature reducing		135		°C
T_{SHUT_HYS}	Thermal shutdown hysteresis			20		°C
t_{SHUT_RDEG}	Thermal shutdown rising deglitch			100		µs
t_{SHUT_FHYS}	Thermal shutdown falling deglitch			12		ms
VSYS PROCHOT COMPARATOR
V_{SYS_PROCHOT}	V_SYS threshold falling threshold	Reg0x36[7:6] = 00, 1 s		2.85		V
		Reg0x36[7:6] = 00, 2–4 s		5.75		V
		Reg0x36[7:6] = 01, 1 s	2.95	3.1	3.25	V
		Reg0x36[7:6] = 01, 2–4 s	5.8	5.95	6.1	V
		Reg0x36[7:6] = 10, 1 s		3.3		V
		Reg0x36[7:6] = 10, 2–4 s		6.25		V
		Reg0x36[7:6] = 11, 1 s		3.5		V
		Reg0x36[7:6] = 11, 2–4 s		6.5		V
t_{SYS_PRO_RISE_DEG}	V_SYS rising deglitch for throttling			8		µs
ICRIT PROCHOT COMPARATOR
V_{ICRIT_PRO}	Input current rising threshold for throttling as percentage above ILIM2 (REG0x33[15:11])	Reg0x36[15:11] = 00000	105%	110%	116%
		Reg0x36[15:11] = 01001	142%	150%	155%
		Reg0x36[15:11] = 11110	410%	430%	455%
INOM PROCHOT COMPARATOR
V_{INOM_PRO}	INOM rising threshold as percentage of IIN (REG0x3F())		105%	110%	116%
IDCHG PROCHOT COMPARATOR
V_{IDCHG_PRO}	IDCHG threshold for throttling for IDSCHG of 6 A	Reg0x38 [15:10]=001100		6144		mA
V_{IDCHG_PRO}	IDCHG threshold for throttling for IDSCHG of 6 A	Reg0x38 [15:10]=001100	95%		102%
INDEPENDENT COMPARATOR
V_{INDEP_CMP}	Independent comparator threshold	Reg0x30[7] = 1, CMPIN falling	1.17	1.2	1.23	V
V_{INDEP_CMP}	Independent comparator threshold	Reg0x30[7] = 0, CMPIN falling	2.27	2.3	2.33	V
V_{INDEP_CMP_HYS}	Independent comparator hysteresis	Reg0x06[6] = 0, CMPIN falling		100		mV
POWER MOSFET DRIVER
PWM OSCILLATOR AND RAMP
F_SW	PWM switching frequency	Reg0x00[9] = 0	1020	1200	1380	kHz
F_SW	PWM switching frequency	Reg0x00[9] = 1	680	800	920	kHz
BATFET GATE DRIVER (BATDRV)
V_{BATDRV_ON}	Gate drive voltage on BATFET		8.5	10	11.5	V
V_{BATDRV_DIODE}	Drain-source voltage on BATFET during ideal diode operation			30		mV
R_{BATDRV_ON}	Measured by sourcing 10-µA current to BATDRV		3	4	6	kΏ
R_{BATDRV_OFF}	Measured by sinking 10-µA current from BATDRV			1.2	2.1	kΏ
PWM HIGH SIDE DRIVER (HIDRV Q1)
R_{DS_HI_ON_Q1}	High side driver (HSD) turnon resistance	V_BTST1 – V_SW1 = 5 V		6		Ω
R_{DS_HI_OFF_Q1}	High side driver turnoff resistance	V_BTST1 – V_SW1 = 5 V		1.3	2.2	Ω
V_{BTST1_REFRESH}	Bootstrap refresh comparator falling threshold voltage	V_BTST1 – V_SW1 when low side refresh pulse is requested	3.2	3.7	4.6	V
PWM HIGH SIDE DRIVER (HIDRV Q4)
R_{DS_HI_ON_Q4}	High side driver (HSD) turnon resistance	V_BTST2 – V_SW2 = 5 V		6		Ω
R_{DS_HI_OFF_Q4}	High side driver turnoff resistance	V_BTST2 – V_SW2 = 5 V		1.5	2.4	Ω
V_{BTST2_REFRESH}	Bootstrap refresh comparator falling threshold voltage	V_BTST2 – V_SW2 when low side refresh pulse is requested	3.3	3.7	4.6	V
PWM LOW SIDE DRIVER (LODRV Q2)
R_{DS_LO_ON_Q2}	Low side driver (LSD) turnon resistance	V_BTST1 – V_SW1 = 5.5 V		6		Ω
R_{DS_LO_OFF_Q2}	Low side driver turnoff resistance	V_BTST1 – V_SW1 = 5.5 V		1.7	2.6	Ω
PWM LOW SIDE DRIVER (LODRV Q3)
R_{DS_LO_ON_Q3}	Low side driver (LSD) turnon resistance	V_BTST2 – V_SW2 = 5.5 V		7.6		Ω
R_{DS_LO_OFF_Q3}	Low side driver turnoff resistance	V_BTST2 – V_SW2 = 5.5 V		2.9	4.6	Ω
INTERNAL SOFT START During Charge Enable
SSSTEP_DAC	Soft Start Step Size			64		mA
SSSTEP_DAC	Soft Start Step Time			8		µs
INTEGRATED BTST DIODE (D1)
V_{F_D1}	Forward bias voltage	I_F = 20 mA at 25°C		0.8		V
V_{R_D1}	Reverse breakdown voltage	I_R = 2 µA at 25°C			20	V
INTEGRATED BTST DIODE (D2)
V_{F_D2}	Forward bias voltage	I_F = 20 mA at 25°C		0.8		V
V_{R_D2}	Reverse breakdown voltage	I_R = 2 µA at 25°C			20	V
PWM DRIVERS TIMING
INTERFACE
LOGIC INPUT (SDA, SCL)
V_{IN_ LO}	Input low threshold	SMBus			0.8	V
V_{IN_ HI}	Input high threshold	SMBus (bq25708)	2.1			V
LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)
V_{OUT_ LO}	Output saturation voltage	5-mA drain current			0.4	V
V_{OUT_ LEAK}	Leakage current	V = 7 V	–1		1	mA
LOGIC OUTPUT OPEN DRAIN SDA
V_{OUT_ LO_SDA}	Output Saturation Voltage	5 mA drain current			0.4	V
V_{OUT_ LEAK_SDA}	Leakage Current	V = 7V	–1		1	mA
LOGIC OUTPUT OPEN DRAIN CHRG_OK
V_{OUT_ LO_CHRG_OK}	Output Saturation Voltage	5 mA drain current			0.4	V
V_{OUT_ LEAK _CHRG_OK}	Leakage Current	V = 7V	–1		1	mA
LOGIC OUTPUT OPEN DRAIN CMPOUT
V_{OUT_ LO_CMPOUT}	Output Saturation Voltage	5 mA drain current			0.4	V
V_{OUT_ LEAK _CMPOUT}	Leakage Current	V = 7V	–1		1	mA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
V_{OUT_ LO_PROCHOT}	Output saturation voltage	50-Ω pullup to 1.05 V / 5-mA load			300	mV
V_{OUT_ LEAK_PROCHOT}	Leakage current	V = 5.5 V	–1		1	mA
ANALOG INPUT (ILIM_HIZ)
V_{HIZ_ LO}	Voltage to get out of HIZ mode	ILIM_HIZ pin rising	0.8			V
V_{HIZ_ HIGH}	Voltage to enable HIZ mode	ILIM_HIZ pin falling			0.4	V
ANALOG INPUT (CELL_BATPRESZ)
V_{CELL_4S}	4S	REGN = 6 V, as percentage of REGN	68.4%	75%
V_{CELL_3S}	3s	REGN = 6 V, as percentage of REGN	51.7%	55%	65%
V_{CELL_2S}	2S	REGN = 6 V, as percentage of REGN	35%	40%	49.1%
V_{CELL_1S}	1S	REGN = 6 V, as percentage of REGN	18.4%	25%	31.6%
V_{CELL_BATPRESZ_RISE}	Battery is present		18%
V_{CELL_BATPRESZ_FALL}	Battery is removed	CELL_BATPRESZ falling			15%
ANALOG INPUT (COMP1, COMP2)
I_{LEAK_COMP1}	COMP1 Leakage		–120		120	nA
I_{LEAK_COMP2}	COMP2 Leakage		–120		120	nA

7.6 Timing Requirements

		MIN	TYP	MAX	UNIT
SMBus TIMING CHARACTERISTICS
t_r	SCLK/SDATA rise time			1	µs
t_f	SCLK/SDATA fall time			300	ns
t_W(H)	SCLK pulse width high	4		50	µs
t_W(L)	SCLK Pulse Width Low	4.7			µs
t_SU(STA)	Setup time for START condition	4.7			µs
t_H(STA)	START condition hold time after which first clock pulse is generated	4			µs
t_SU(DAT)	Data setup time	250			µs
t_H(DTA)	Data hold time	300			µs
t_SU(STOP)	Setup time for STOP condition	4			µs
t_(BUF)	Bus free time between START and STOP condition	4.7			µs
F_S(CL)	Clock Frequency	10		100	KHz
HOST COMMUNICATION FAILURE
t_timeout	SMBus bus release timeout⁽¹⁾	25		35	ms
t_BOOT	Deglitch for watchdog reset signal	10			ms
t_WDI	Watchdog timeout period, ChargeOption() bit [14:13] = 01⁽²⁾	35	44	53	s
	Watchdog timeout period, ChargeOption() bit [14:13] = 10⁽²⁾	70	88	105	s
	Watchdog timeout period, ChargeOption() bit [14:13] = 11⁽²⁾ (default)	140	175	210	s

(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).

(2) User can adjust threshold via SMBus ChargeOption() REG0x12.