ZHCSNB8A February 2021 – January 2024 BQ25730
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_CONV | ADC_START | ADC_FULLSCALE | Reserved | ||||
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_ADC_CMPIN | EN_ADC_VBUS | EN_ADC_PSYS | EN_ADC_IIN | EN_ADC_IDCHG | EN_ADC_ICHG | EN_ADC_VSYS | EN_ADC_VBAT |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC is disabled in low power mode. Before enabling ADC, low power mode should be disabled first.
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | ADC_CONV | R/W | 0b | Typical each ADC channel
conversion time is 25 ms maximum. Total ADC conversion time is the
product of 25 ms and enabled channel counts. 0b: One-shot update. Do one set of conversion updates to registers REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C() after ADC_START = 1. 1b: Continuous update. Do a set of conversion updates to registers REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C()every 1 sec. |
| 6 | ADC_START | R/W | 0b | 0b: No ADC conversion 1b: Start ADC conversion. After the one-shot update is complete, this bit automatically resets to zero |
| 5 | ADC_FULLSCALE | R/W | 1b | ADC input voltage range adjustment for PSYS and CMPIN ADC Channels. 2.04-V full scale holds 8 mV/LSB resolution and 3.06-V full scale holds 12 mV/LSB resolution 0b: 2.04 V 1b: 3.06 V <default at POR>(Not accurate for REGN<6-V application (VBUS & VSYS< 6V)) |
| 4-0 | Reserved | R/W | 00000b | Reserved |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | EN_ADC_CMPIN | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
| 6 | EN_ADC_VBUS | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
| 5 | EN_ADC_PSYS | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
| 4 | EN_ADC_IIN | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
| 3 | EN_ADC_IDCHG | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
| 2 | EN_ADC_ICHG | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
| 1 | EN_ADC_VSYS | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
| 0 | EN_ADC_VBAT | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |