Output capacitor also should have enough ripple current rating to absorb output switching ripple current. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25-V X7R or X5R for output capacitor. Minimum 7 pcs of 10-μF 0603 package capacitor is suggested to be placed as close as possible to Q3&Q4 half bridge (between Q4 drain and Q3 source terminal). Total minimum output effective capacitance along VSYS distribution line is 50 μF refers to Table 9-1. Recommend to place minimum 20-μF MLCC capacitors after the charge current sense resistor for best stability.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required capacitance value at the operating point. Considering the 25-V 0603 package MLCC capacitance derating under 21-V to 23-V output voltage, the recommended practical capacitors configuration at VSYS output terminal can also be found in Table 9-1. Tantalum capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which are recommend to be used along VSYS output distribution line to meet total minimum effective output capacitance requirement.