The ACK signaling takes place after byte. The ACK bit allows the target to signal the controller that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9^th clock pulse, are generated by the controller.

The controller releases the SDA line during the acknowledge clock pulse so the target can pull the SDA line LOW and it remains stable LOW during the HIGH period of this 9^th clock pulse.

A NACK is signaled when the SDA line remains HIGH during the 9^th clock pulse. The controller can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.