SLUSFH5A May 2024 – October 2024 BQ25856-Q1
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
The DRV_SUP pin must maintain a valid voltage between DRV_UVP and DRV_OVP for proper operation of the switching power converter stage. This is true both in charging mode and in reverse mode.
When DRV_SUP pin voltage falls below DRV_UVP threshold, the switching converter stops operation, an INT pulse is asserted to signal the host, the DRV_OKZ_STAT, and DRV_OKZ_FLAG bits are set to signal the fault. Additionally, the STAT1 and STAT2 pins will change to reflect the charger function is disabled.
When DRV_SUP pin voltage rises above DRV_OVP threshold, the switching converter stops operation, an INT pulse is asserted to signal the host, the DRV_OKZ_STAT, and DRV_OKZ_FLAG bit are set to signal the fault. Additionally the STAT1 and STAT2 pins will change to reflect the charger function is disabled.
When the DRV pin returns to normal operating range, the device automatically resumes switching in either charging or reverse mode as configured before the fault.