11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loops is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

1. Place SYS and BAT output capacitor as close to SYS, BAT and GND bumps as possible. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
2. Place PMID input capacitor as close as possible to PMID bumps and GND bumps and use shortest copper trace connection or GND plane.
3. Place inductor input terminal to SW bumps as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the input current. Minimize parasitic capacitance from this area to any other trace or plane.
4. Decoupling capacitors should be placed next to the IC and make trace connection as short as possible.
5. Ensure that there are sufficient thermal vias directly under bumps of the power FETs, connecting to copper on other layers.
6. Via size and number should be enough for a given current path.
7. Route BATP and BATN away from switching nodes such as SW.

Refer to the EVM design and the Layout Example below for the recommended component placement with trace and via locations.